A slight correction (I made it earlier but didn't highlight it): 5a is also
used for Thumb code, as "5a -t" to restrict the input to thumb
constructions and tag the output as Thumb code (using .t files instead of
.5)
The thumb mkfile sets AS=5a -t
Since the Thumb-2 changes aren't supported, and it's the original Thumb, I
think that makes the supported architecture Armv6-M in current
documentation terms.
It looks to me as though it would work on Cortex M0, but I think the thumb
mode was only ever used by us on ARM's little Armv7-t Evaluator board,
which I can't even find documented now.
Normally even that board ran in (normal) ARM32 mode. The Thumb work on it
was just a stepping stone for using Thumb mode on a proprietary 3rd party
ARM implementation, although even there it was probably experimental.
Inferno can run without an MMU. Even given an MMU it sets a fairly flat map
across physical memory and the MMU functionality is mainly used to map
devices.
The os/ks32 directory is a guide to squashing the system down to fit modest
if not tiny memory (again, in ARM32 mode).

On Sat, Nov 7, 2020 at 2:24 PM Thaddeus Woskowiak <tswoskowiak@gmail.com>
wrote:

> On Thu, Nov 5, 2020 at 7:12 PM Charles Forsyth
> <charles.forsyth@gmail.com> wrote:
> >
> > There was a 5[ac] variant for Inferno (ta, tc) that produced Thumb code,
> and 5l could link Thumb and ARM32 code.
> > That wasn't extended once Thumb-2 was issued, since it was different
> enough to require a fair amount of work and we had no immediate application
> on the Cortex.
> >
> >
> > On Thu, Nov 5, 2020 at 11:38 PM Thaddeus Woskowiak <
> tswoskowiak@gmail.com> wrote:
> >>
> >> I would like to know if anyone is working on or exists an Arm Thumb
> >> compiler so one could use plan 9 to program Arm Cortex M0/3/4/7
> >> microcontrollers directly. I know of Charles Forsyth's xc AVR compiler
> >> which is also interesting. Though I have yet to try it out.
> >>
> >> -taw
> >
> > 9fans / 9fans / see discussions + participants + delivery options
> Permalink
> 
> Charles, Thank you for the information. So Thumb compiling and
> assembly is handled by tc and ta respectively while 5l can handle
> linking both thumb code and arm 32.
> 
> I guess my next question is: does this mean Inferno can run on certain
> Cortex-M micros since it can run MMU-less? (provided enough memory of
> course) And has this been done before?

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