From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Tue, 4 Mar 2008 10:00:50 -0800 From: "Roman V. Shaposhnik" Subject: Re: [9fans] GCC/G++: some stress testing In-reply-to: <9f3897940803040257i67b7b8ccp3e60eb1b1236d5a8@mail.gmail.com> To: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu> Message-id: <1204653650.27006.322.camel@goose.sun.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 References: <1204515076.27006.173.camel@goose.sun.com> <9f3897940803040257i67b7b8ccp3e60eb1b1236d5a8@mail.gmail.com> Content-Transfer-Encoding: quoted-printable Topicbox-Message-UUID: 6eb9a042-ead3-11e9-9d60-3106f5b1d025 On Tue, 2008-03-04 at 11:57 +0100, Pawe=C5=82 Lasek wrote: > > I take it that you really do mean "simultaneous". As in: you actuall= y > > have hundreds of cores available on the same system. I'm actually > > quite curious to find out what's the highest number of cores availab= le > > of a single shared memory systems that you, or anybody else has > > experienced in practice so far (mine would be 32 =3D=3D 8 CPUs x 4 c= ores AMD > > Barcelona)? Now even more important question is -- what are the > > expectations for, this number in 5 years from now? > > >=20 > Actually, with parts available from AMD you can directly mesh up to 64 > sockets, each with (currently) 4 cores, 8 core cpu announced (as MCP > in the beginning). And there were available methods for routing HT > traffic with number of sockets nearing thousands or tens of thousands. > Dunno if they used it directly with cache coherency protocol though. Understood. Although, what I meant was a practical hands-on experience. So that the war stories can be told. Otherwise, on the SPARC side, I'd be able to claim 128 in Sun's M9000. Thanks, Roman.