From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Mon, 2 Jun 2008 15:22:01 -0700 From: Roman Shaposhnik In-reply-to: <13426df10806021455o21bcda47s65e51fb2e194a797@mail.gmail.com> To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Message-id: <1212445321.4280.1085.camel@work.sfbay.sun.com> MIME-version: 1.0 Content-type: text/plain Content-transfer-encoding: 7BIT References: <13426df10806021455o21bcda47s65e51fb2e194a797@mail.gmail.com> Cc: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu> Subject: Re: [9fans] when is a branch not a branch? Topicbox-Message-UUID: b24bdab4-ead3-11e9-9d60-3106f5b1d025 On Mon, 2008-06-02 at 14:55 -0700, ron minnich wrote: > now I time the run 10 times (I can run longer but it seems good enough > to establish behavior). I should get some rough idea of the cost of > the branch. I hate to say it: but these days you can't time anything in isolation. The CPU is just too complex. It is no longer an x86, really. The microcode is what you have to worry about. And how the microinstructions get scheduled, and how they interact with each other, etc. etc. You wouldn't believe the kind of crazy stuff that sometimes you see in the x86 compiler optimization team here at Sun. So, unless your actual code is exactly like the benchmark you quoted -- the results could be completely off. I talk from experience. The experience of SPEC. Thanks, Roman. P.S. With the modern CPUs even the most basic of questions could turn out to be quite surprising. I'm still shocked that even by utilizing some of the close ties to Intel/AMD I wasn't able to find an *authoritative* source on information on a very basic thing: cache architecture for modern x86 CPUs. Well, everybody assume that they know: http://people.redhat.com/drepper/cpumemory.pdf how the cache operates (e.g. what is the "hash function" for the virtual/physical address, etc.) but none of the documentation from Intel/AMD explicitly confirms that.