From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 In-Reply-To: <20091019152602.GA13857@nipl.net> References: <4030fb6ae37f8ca8ae9c43ceefbdf57b@ladd.quanstro.net> <20091016172030.GB3135@nipl.net> <20091019152602.GA13857@nipl.net> Date: Mon, 19 Oct 2009 08:50:40 -0700 Message-ID: <13426df10910190850q937f4f3x7afe383abbeb1a66@mail.gmail.com> From: ron minnich To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: text/plain; charset=ISO-8859-1 Subject: Re: [9fans] Barrelfish Topicbox-Message-UUID: 8b4bb6b2-ead5-11e9-9d60-3106f5b1d025 On Mon, Oct 19, 2009 at 8:26 AM, Sam Watkins wrote: > On Fri, Oct 16, 2009 at 12:18:47PM -0600, Latchesar Ionkov wrote: >> How do you plan to feed data to these 31 thousand processors so they >> can be fully utilized? Have you done the calculations and checked what >> memory bandwidth would you need for that? > > I would use a pipelining + divide-and-conquer approach, with some RAM on chip. > Units would be smaller than a 6502, more like an adder. I'm not convinced. Lucho just dropped a well known hard problem in your lap (one he deals with every day) but your reply sounds like handwaving. This stuff is harder than it sounds. Unless you're ready to come up with a simulation of your claim -- and it had better be a pretty good one -- I don't think anybody is going to be buying. If you're going to just have adders, for example, you're going to have to explain where the instruction sequencing happens. If there's only one sequencer, then you're going to have to explain why you have not just reinvented the CM-2 or similar MPP. Again, this stuff is quantifiable. A pipeline implies a clock rate. Divide and conquer implies fanout. Where are the numbers? ron