From mboxrd@z Thu Jan 1 00:00:00 1970 Message-Id: <1536154535.3101424.1497581560.1364EF09@webmail.messagingengine.com> From: Ethan Gardener To: 9fans@9fans.net MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" References: In-Reply-To: Date: Wed, 5 Sep 2018 14:35:35 +0100 Subject: Re: [9fans] Is Plan 9 C "Less Dangerous?" Topicbox-Message-UUID: e11b5314-ead9-11e9-9d60-3106f5b1d025 On Wed, Sep 5, 2018, at 12:42 PM, Chris McGee wrote: > > They even built their own high level hardware language (Chisel) that generates Verilog using Scala. Yuck. >>From what I've heard of Verilog and VHDL, this is the sane approach. I only have second hand knowledge of these languages, my source is a guy who wrote his own language to compile to Verilog. :) > Could you get away with a much simpler, smaller hardware design and still run Plan 9 in a reasonable way? They did while developing Plan 9. (sorry :) Complex hardware just makes it easier to get higher performance. > Maybe one side of the software/hardware divide has to take on more complexity to help simplify the other side? I think so, and not just at that one divide. I tried designing an 8-bit CPU, but found I had to make complicated decisions to cram a reasonable instruction set into just 8 bits. I would need a broad and deep knowledge set to make good choices. Then there's Plan 9's file interface, where there's very few operations and they're very easy to use, but I think it must have required a lot of experience and careful design to choose the semantics which make those operations so easy to use. A lot of Plan 9's simplicity is like that, it took experience and careful thought to make those simple interfaces and write that seemingly simple code. -- The lyf so short, the craft so long to lerne. -- Chaucer