From mboxrd@z Thu Jan 1 00:00:00 1970 Date: Mon, 21 Aug 1995 10:07:55 -0400 From: jmk@plan9.att.com jmk@plan9.att.com Subject: SPEA Mirage (was: Re: format for source diffs) Topicbox-Message-UUID: 196dfaf8-eac8-11e9-9e20-41e7f4b1d025 Message-ID: <19950821140755.h0dm0dHGwW98fdJQWu2_h_Gf32BM4aWyhx-SHRPv0SE@z> > The SPEA MirageP64 (2MB DRAM) has a: > - S3 86C716 SDAC RAMDAC and Clockchip (BIOS 4.xx) > - 20C498 or 21C498/ICS2595 Clockchip (BIOS 3.xx) > (according to the X11R6/XFree3.1.2 documents) >>From vgadb(6): ADDING A NEW VGA CONTROLLER While the use of this database formalizes the steps needed to program a VGA controller, unless you are very lucky and all the important components on a new VGA controller card are interconnected in the same way as an existing entry, adding a new entry requires adding new internal types to vga(8). At a minimum you will need the data sheets for the VGA con- troller chip, the RAMDAC and the clock generator. You will also need to know how these components interact. For exam- ple, a common combination is an S3 86C928 VGA chip with an ICD2061A clock generator. The ICD2061A is usually loaded by clocking a serial bit-stream out of one of the 86C928 regis- ters. Similarly, the RAMDAC may have an internal clock- doubler and/or pixel-multiplexing modes, in which case both the clock generator and VGA chip must be programmed accord- ingly. Neither of the SPEA Mirage variants above is completely described by the current aux/vga and database. I don't have a datasheet for the 86C716 but that would likely be the more stable of the to two try programming, there's obviously less room for maneuver connecting 2 chips together compared to 3 using the 21C498+ICS2595 combination. However, the 21C498 is already handled by aux/vga and the 2595 looks straightforward from the datasheet (although it's programmable, it has a default table which might suffice).