* SPEA Mirage (was: Re: format for source diffs)
@ 1995-09-09 13:33 Stefan
0 siblings, 0 replies; 4+ messages in thread
From: Stefan @ 1995-09-09 13:33 UTC (permalink / raw)
Hi,
this patch to aux/vga works fine with my Spea Mirage. The entry
for the `GIS Globalyst 550' also matches my card, so I had to remove it.
The patch is relative to the cd distribution.
Stefan
============================================
% diff new /sys/src/cmd/aux/vga/vgadb
47,52d46
< 0xC00E4="V7-MIRAGE P-64 BIOS Version 4" # Spea Mirage Bios 4.xx
< link=vga
< hwgc=s3hwgc
< ctlr=vision864 link=ibm8514
< ramdac=s3sdac
< ctlr
54c48
< # 0xC0044="Phoenix S3 Vision864 (16Bit DAC)" # GIS Globalyst 550
---
> 0xC0044="Phoenix S3 Vision864 (16Bit DAC)" # GIS Globalyst 550
============================================
% diff new /sys/src/cmd/aux/vga/data.c
31d30
< &s3sdac, /* ramdac & clock */
============================================
% diff new /sys/src/cmd/aux/vga/mkfile
29d28
< s3sdac.$O\
============================================
% diff new /sys/src/cmd/aux/vga/vga.h
221,223d220
< /* s3sdac.c */
< extern Ctlr s3sdac;
<
============================================
% diff new /sys/src/cmd/aux/vga/vision864.c
50c50,51
< * magic formula below is taken from XFree86.
---
> * values below are guesses from dumping
> * registers.
56,74c57,62
< {
< long m, n, clk, mclk;
< clk = vga->f;
< n = 255;
< mclk = 60000000;
< if (vga->vmb < 2048*1024)
< clk *= 2;
< m = (mclk*.72+16867000)*89.736/(clk+39000000)-21;
< if (vga->vmb < 2048*1024)
< m /= 2;
< if (m > 31)
< m = 31;
< if (m < 0) {
< m = 0;
< n = 16;
< }
< vga->crt[0x54] = m<<3;
< vga->crt[0x60] = n;
< }
---
> if(vga->mode->x <= 800)
> vga->crt[0x54] = 0x88;
> else if(vga->mode->x <= 1024)
> vga->crt[0x54] = 0xF8;
> else
> vga->crt[0x54] = 0x40;
75a64
>
78c67
< vga->crt[0x67] |= 0x11;
---
> vga->crt[0x67] |= 0x10;
============================================
% cat /sys/src/cmd/aux/vga/s3sdac.c
#include <u.h>
#include <libc.h>
#include "vga.h"
/*
* S3 SDAC 86C716 RAMDAC and programmable clock.
*/
enum {
PClk = 0x02,
MClk = 0x0a,
};
static void
options(Vga *vga, Ctlr *ctlr)
{
USED(vga);
verbose("%s->options\n", ctlr->name);
ctlr->flag |= Hpclk2x8|Foptions;
}
static void
init(Vga *vga, Ctlr *ctlr)
{
verbose("%s->init\n", ctlr->name);
/*
* If we don't already have a desired pclk,
* take it from the mode.
* Check it's within range.
*/
if(vga->f == 0)
vga->f = vga->mode->frequency;
if(!(vga->f <= 67500000 || ((vga->ctlr->flag & Hpclk2x8) && vga->f <=135000000)))
error("%s: invalid pclk - %ld\n", ctlr->name, vga->f);
/*
* Determine whether to use 2x8-bit mode or not.
* If yes and the clock has already been initialised,
* initialise it again.
*/
if(vga->ctlr && (vga->ctlr->flag & Hpclk2x8) && vga->f >= 67500000)
resyncinit(vga, ctlr, Upclk2x8, 0);
/*
* Calculate n&d.
*/
{
long f, fmin, m, n1, n2;
vga->d = 0;
vga->n = 0;
fmin = vga->f;
for (n1=1; n1<32; ++n1)
for (n2=0; n2<4; ++n2) {
m = vga->f * (n1+2) * (1<<n2) / Frequency - 2;
if (m<1 || m>127)
continue;
if (Frequency * (m+2)/(n1+2) > 250000000 ||
Frequency * (m+2)/(n1+2) < 100000000)
continue;
f = vga->f - (Frequency * (m+2)/(n1+2)/(1<<n2));
if (f < 0)
f = -f;
if (f > fmin)
continue;
fmin = f;
vga->n = m;
vga->d = n1 + (n2<<5);
}
}
ctlr->flag |= Finit;
}
static void
loadsdac(Vga *vga, uchar index, uchar n, uchar d)
{
vgao(MiscW, vga->misc | 0x0c);
vgaxo(Crtx, 0x42, vga->crt[0x42] & ~0x0f | 0x02);
vgaxo(Crtx, 0x55, vga->crt[0x55] & ~0x03 | 0x01);
vgao(PaddrW, index);
vgao(Pdata, n);
vgao(Pdata, d);
vgaxo(Crtx, 0x55, vga->crt[0x55] & ~0x03);
vgaxo(Crtx, 0x42, vga->crt[0x42] & 0xf0 | 0x06);
}
static void
load(Vga *vga, Ctlr *ctlr)
{
verbose("%s->load\n", ctlr->name);
/*
* unlock registers
*/
vgaxo(Crtx, 0x38, 0x48);
vgaxo(Crtx, 0x39, 0xa5);
/*
* set mclk to 60 MHz
*/
loadsdac(vga, MClk, 0x41, 0x42);
/*
* screen off
*/
vgaxo(Seqx, 0x01, vga->sequencer[0x01] | 0x20);
/*
* set command register
*/
vgai(PaddrR);
vgai(Pixmask); vgai(Pixmask); vgai(Pixmask); vgai(Pixmask);
if(ctlr->flag & Upclk2x8)
vgao(Pixmask, 0x10);
else
vgao(Pixmask, 0x00);
vgai(PaddrR);
vgao(Pixmask, 0xff);
/*
* set pclk
*/
loadsdac(vga, PClk, vga->n, vga->d);
/*
* screen on
*/
vgaxo(Seqx, 0x01, vga->sequencer[0x01]);
ctlr->flag |= Fload;
}
Ctlr s3sdac = {
"s3sdac", /* name */
0, /* snarf */
options, /* options */
init, /* init */
load, /* load */
0, /* dump */
};
============================================
^ permalink raw reply [flat|nested] 4+ messages in thread
* SPEA Mirage (was: Re: format for source diffs)
@ 1995-09-09 23:21 jmk
0 siblings, 0 replies; 4+ messages in thread
From: jmk @ 1995-09-09 23:21 UTC (permalink / raw)
Ha! Someone else touched aux/vga!
My work is done.
^ permalink raw reply [flat|nested] 4+ messages in thread
* SPEA Mirage (was: Re: format for source diffs)
@ 1995-08-21 14:07 jmk
0 siblings, 0 replies; 4+ messages in thread
From: jmk @ 1995-08-21 14:07 UTC (permalink / raw)
> The SPEA MirageP64 (2MB DRAM) has a:
> - S3 86C716 SDAC RAMDAC and Clockchip (BIOS 4.xx)
> - 20C498 or 21C498/ICS2595 Clockchip (BIOS 3.xx)
> (according to the X11R6/XFree3.1.2 documents)
>From vgadb(6):
ADDING A NEW VGA CONTROLLER
While the use of this database formalizes the steps needed
to program a VGA controller, unless you are very lucky and
all the important components on a new VGA controller card
are interconnected in the same way as an existing entry,
adding a new entry requires adding new internal types to
vga(8).
At a minimum you will need the data sheets for the VGA con-
troller chip, the RAMDAC and the clock generator. You will
also need to know how these components interact. For exam-
ple, a common combination is an S3 86C928 VGA chip with an
ICD2061A clock generator. The ICD2061A is usually loaded by
clocking a serial bit-stream out of one of the 86C928 regis-
ters. Similarly, the RAMDAC may have an internal clock-
doubler and/or pixel-multiplexing modes, in which case both
the clock generator and VGA chip must be programmed accord-
ingly.
Neither of the SPEA Mirage variants above is completely described by the
current aux/vga and database. I don't have a datasheet for the 86C716 but
that would likely be the more stable of the to two try programming, there's
obviously less room for maneuver connecting 2 chips together compared to
3 using the 21C498+ICS2595 combination. However, the 21C498 is already
handled by aux/vga and the 2595 looks straightforward from the datasheet
(although it's programmable, it has a default table which might suffice).
^ permalink raw reply [flat|nested] 4+ messages in thread
* SPEA Mirage (was: Re: format for source diffs)
@ 1995-08-21 10:10 Markus
0 siblings, 0 replies; 4+ messages in thread
From: Markus @ 1995-08-21 10:10 UTC (permalink / raw)
> (my card is a Spea Mirage S3 with 868 chip and 2MB dram). Anyone know if i
> can patch the vgadb to work with this chip?
>
> the 868 can be described in vgadb as a vision864. i don't know what the clock
> or ramdac is on that board.
The SPEA MirageP64 (2MB DRAM) has a:
- S3 86C716 SDAC RAMDAC and Clockchip (BIOS 4.xx)
- 20C498 or 21C498 RAMDAC, ICS2595 Clockchip (BIOS 3.xx)
(according to the X11R6/XFree3.1.2 documents)
--markus
^ permalink raw reply [flat|nested] 4+ messages in thread
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1995-09-09 13:33 SPEA Mirage (was: Re: format for source diffs) Stefan
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