From mboxrd@z Thu Jan  1 00:00:00 1970
Date: Wed, 10 Dec 1997 10:50:48 -0600
From: G. David Butler gdb@dbSystems.com
Subject: [9fans] Re: Plan 9 from Bell Labs - Frequently Asked
Topicbox-Message-UUID: 6cf08574-eac8-11e9-9e20-41e7f4b1d025
Message-ID: <19971210165048.Q9Gy1CEKkr2i0rj7eHFCvXZd2y45C6z6PPd8ifvgHSc@z>

>which of the above cards are you classifying as 32-bit?
>the 579 and 597 are 32-bit (eisa).  we have 579s and they work fine.
>the 597 probably won't work without dealing with various chip errata.

I didn't have the piece of information that "Large packet support
affects bit-field widths in the following registers: RxStatus,
MasterStatus, TxStartThresh, TxAvailableThresh and RxEarlyThresh".
My 579s now work fine, too.

>the 905 is problematic: although it has compatibility with the older
>cards the fifos are tiny and the card really has to be run in
>busmastering mode or it gums up a lot (it works well enough in fifo
>mode to boot a kernel with b.com though).

Mine seems to work in PIO mode.  I don't see any receive overruns
when pushed and I can easily keep the transmit FIFO full.

>                                           in busmastering mode there
>are chip errata which have to be dealt with or it can hang up too.

You mean like you have to set the latency timer to 0xFF?

>as i mentioned in a previous message i still have problems with the
>905 so i'm interested in any other experiences with it.

I'm trying to get it to work reliably too.  I don't have the
right documentation for PCI to know how to set the busmaster bit
or to set the latency timer as specified by the errata.
Can you help here?