Re: [9fans] Toshiba Tecra 720 (notebook)

[okamoto@granite.cias.osakafu-u.ac.jp]

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>In fact, commands are sent safely to FDC, and I get right results other
>than floppyxfer() which uses DMA transfer.

When I'm reading japanese documentation on υPD765 FDC chip, I found
this chip requires response from the CPU within a relatively short time
period, such that 14υS.  If there is no such response from the CPU,
it goes to overrun error.  Does the Plan 9 DMA mechanism can satisfy
this demand?

Kenji


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From: okamoto@granite.cias.osakafu-u.ac.jp
To: 9fans@cse.psu.edu
Subject: Re: [9fans] Toshiba Tecra 720 (notebook)
Date: Tue, 9 Jan 2001 19:22:43 0900
Message-ID: <20010109102301.08D8D19A45@mail.cse.psu.edu>

nclude: /mail/fs/mbox/55/raw

Well,... I'm still here (too much anxious to leave from here).

I suspected this Toshiba machine may use NEC's υPD765 FDC, and got a
document on this chip from net 
(http://www.htl-steyr.ac.st/_morg/pcinfo/hardware/interrupts/hard0001.html),
 and found a command (just 0x10) to check what is the name of this FDC chip 
which works only for these NEC's υPD765 families.

Then, I tested this, and got the FDC of this Toshiba Tecra 720 is NEC's 
υPD765A or υPD765A-2.  This means that we have no means to control 
floppy motor rotation speed from this chip, which should be there outside 
the chip.  However, I may not be facing this problem now(I'm not sure).

The document says this FDC chip is not different from the coded one in
/sys/src/9/pc/devfloppy.c where I cannot find any problem sofar.
In fact, commands are sent safely to FDC, and I get right results other
than floppyxfer() which uses DMA transfer.

Are there any recommendation to check if this is just the problem
whichi I'm facing.

Anyway, the document says "INT 6 sets bit 7 of BIOS Data Area location 40:3E
which can be polled for completion status."  Is this also right for Plan 9 kernel?

Kenji