From mboxrd@z Thu Jan 1 00:00:00 1970 From: jmk@plan9.bell-labs.com To: 9fans@cse.psu.edu Subject: Re: [9fans] how people learn things (was architectures) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Message-Id: <20010713163252.E5AAD199C0@mail.cse.psu.edu> Date: Fri, 13 Jul 2001 12:32:50 -0400 Topicbox-Message-UUID: cccd69e8-eac9-11e9-9e20-41e7f4b1d025 Please, lighten up. There's no point in raking over this stuff again and again. All architectures have had their missteps, even the venerable PDP-11. As Phil Winterbottom said when Ken Thompson was bemoaning the demise of Mips Technologies and the coming age of all the world's a 386 - they won, we lost, get over it. IA32 'superservers' can address >4GB of PHYSICAL memory due to page-table extensions, it's nothing to do with segmentation and doesn't need to be written in assembler. On Fri Jul 13 12:21:25 EDT 2001, lucio@proxima.alt.za wrote: > On Fri, Jul 13, 2001 at 03:26:08PM +0000, Douglas A. Gwyn wrote: > > > > Lucio De Re wrote: > > > No more than from Intel (they are to be blamed for CP/M, too), > > > overlooking the fact that their address bus was wider than the > > > register size, or scrapping the i860/i960 developments. > > > They are rushed decisions that can't be reversed. ... > > > > Even the original PDP-11 had a wider address bus than its > > register (word) size. It wasn't a "rushed decision", although > > in the long run it caused enough trouble that a whole new > > architecture was designed to replace it. > > Do you mean to tell me that DEC had a segmented architecture, with > haphazard default "base" registers, a LOCK instruction to lock the > bus for the following fetch cycle (whatever for? even the Univac > 1106 had the more sane test-and-set) and a faulty MOV SS,XX that > did _not_ lock the bus for the following MOV SP,YY as was the > intention? > > I bet the 20-bit address was an oversight, one that is still being > dragged along in this era of 64-bit registers. For heaven's sake, > Intel's marketing hype was full of praise for the ability to have > 2^12 (overlapping) segments, and to this day the Pentium has segment > registers. Worse, one reads of superservers addressing up to > 64Gigabytes of main memory - must be programmed in assembler 'cause > it's a long time since I've seen a compiler capable of producing > segmented architecture code. > > > architecture was designed to replace it. > > No, not to "replace it", but to propagate it. > > ++L