oh yes, i'd forgotten about the Clipper.
i did Ka Kc and Kl for the Fairchild/Intergraph Clipper chip in a week
(1992/3 Plan 9), but i wasn't working very hard.  the Plan 9 assembler
is nearly always at most an afternoon's effort.  the time for the
compiler varies quite a bit.  the Clipper architecture was
straightforward.  the compiler was easy.
most of the time was spent on the linker.  Kl got to
compensate for all the processor pipeline/scoreboard bugs.  dreadful.
nice architecture but buggy implementation.