From mboxrd@z Thu Jan  1 00:00:00 1970
Message-Id: <200603071747.k27HlVJ0093118@gate.bitblocks.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu>
From: Bakul Shah <bakul+plan9@BitBlocks.com>
Subject: Re: [9fans] structure allocation.
In-reply-to: Your message of "Mon, 06 Mar 2006 20:13:44 PST."
	<fa0b319554446f7fb9c720fab239eb31@collyer.net>
Date: Tue,  7 Mar 2006 09:47:31 -0800
Topicbox-Message-UUID: 0de15ee2-ead1-11e9-9d60-3106f5b1d025

> It sounds like the folks who designed the dac960 either didn't think
> much about how drivers would access it, or they were hog wild over
> gcc's packed data attribute (does microsoft's compiler have something
> similar?).

I suspect that as usual either the h/w designers weren't
thinking about the driver guys or didn't listen to them, or
the driver guys didn't come on board until after the "design
was done".  The h/w logic is probably doing the equivalent of

	for (i = 0; i < 10; i++) {
		data_bus <= byte[i];
		assert ready;
		wait ack;
	}

In the scheme of things this particular register layout may
have come about because that is how the design evolved or it
was an arbitrary choice or it minimized the number of logic
gates to fit in the fewest number of PALs (likely the DAC960
still carries some logic originally designed for a board full
of PALs and what not).