From: Dan Cross <cross@math.psu.edu>
To: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu>
Subject: Re: [9fans] usb keyboard and mouse?
Date: Thu, 29 Jun 2006 07:55:31 -0400 [thread overview]
Message-ID: <20060629115531.GB5893@augusta.math.psu.edu> (raw)
In-Reply-To: <200606290531.k5T5VQ1W000476@ducky.net>
On Wed, Jun 28, 2006 at 10:31:26PM -0700, Mike Haertel wrote:
> The implementation is chipset dependent. Often what happens is
> that the chipset recognizes an I/O request to port 0x60 or 0x64 and
> aborts the request with an SMI (system management interrupt). This
> is a *very* non-maskable interrupt (more non-maskable than NMI...)
> that causes the processor to save pretty much all its register state
> in a special memory area, and jump to a handler in the system BIOS.
> The BIOS SMI handler examines the saved register state, figures out
> what the OS was trying to do, runs a software model of the PS/2
> keyboard controller's state, chats with the USB keyboard, formulates
> an appropriate response, emulates the I/O instruction the OS was
> trying to do, and resumes execution of the OS at the instruction
> following the I/O instruction.
>
> Some chipsets might do it directly in hardware rather than using
> the SMI+BIOS strategy.
Dear Lord! At what point is a chicken sacrificed in this process?
- Dan C.
next prev parent reply other threads:[~2006-06-29 11:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-29 5:31 Mike Haertel
2006-06-29 8:23 ` Charles Forsyth
2006-06-29 11:55 ` Dan Cross [this message]
2006-06-29 15:02 ` Ronald G Minnich
2006-06-29 23:50 ` Charles Forsyth
-- strict thread matches above, loose matches on Subject: below --
2006-06-26 18:50 ISHWAR RATTAN
2006-06-26 19:22 ` Francisco J Ballesteros
2006-06-27 0:19 ` geoff
2006-06-28 15:48 ` Artem Letko
2006-06-28 17:01 ` Francisco J Ballesteros
2006-06-28 23:02 ` C H Forsyth
2006-06-28 23:21 ` Ronald G Minnich
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