From: William Josephson <jkw@eecs.harvard.edu>
To: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu>
Subject: Re: [9fans] non-PC hardware
Date: Wed, 28 Mar 2007 00:19:35 -0400 [thread overview]
Message-ID: <20070328041935.GA17989@mero.morphisms.net> (raw)
In-Reply-To: <949f4efc668a768d724d2b5399f49e7a@coraid.com>
On Tue, Mar 27, 2007 at 08:06:22PM -0400, erik quanstrom wrote:
> i'm not sure what advantage more registers present in modern (amd|intel)/x64
> chips. a value in l1 cache is only 1 cycle away. so i'm not sure what the
> practical difference is between something in a register and something in l1.
It is more than 1 cycle away; more like 2-3 and for many
applications the extra registers do make a big difference.
next prev parent reply other threads:[~2007-03-28 4:19 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-03-27 20:31 maht
2007-03-27 20:41 ` John Floren
2007-03-27 20:43 ` ron minnich
2007-03-27 20:54 ` Lorenzo Fernando Bivens de la Fuente
2007-03-27 21:09 ` Paul Lalonde
2007-03-27 21:57 ` ron minnich
2007-03-27 22:05 ` Paul Lalonde
2007-03-27 20:56 ` John Floren
2007-03-27 20:58 ` erik quanstrom
2007-03-28 15:42 ` Iruata Souza
2007-03-28 16:05 ` Jack Johnson
2007-03-28 16:14 ` David Arnold
2007-03-28 16:14 ` andrey mirtchovski
2007-03-28 16:19 ` andrey mirtchovski
2007-03-28 17:09 ` erik quanstrom
2007-03-28 17:22 ` Sape Mullender
2007-03-28 16:21 ` Francisco J Ballesteros
2007-03-28 16:36 ` Jack Johnson
2007-03-28 16:18 ` Tim Wiess
2007-03-29 10:55 ` Harri Haataja
2007-03-29 13:12 ` erik quanstrom
2007-03-27 23:34 ` Lawrence E. Bakst
2007-03-28 0:06 ` erik quanstrom
2007-03-28 4:19 ` William Josephson [this message]
2007-03-28 13:29 ` Charles Forsyth
2007-03-28 0:11 ` David Arnold
2007-03-28 9:28 ` Anel Philippe
[not found] ` <p0624081bc22f52bb96dd@192.168.127.192>
2007-03-28 16:14 ` Lluís Batlle
2007-03-28 16:17 ` Tim Wiess
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