From mboxrd@z Thu Jan  1 00:00:00 1970
From: dexen deVries <dexen.devries@gmail.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
Date: Fri, 10 Jan 2014 13:36:40 +0100
Message-ID: <2094025.eXPNWkS2km@coil>
User-Agent: KMail/4.10.5 (Linux/3.12.0-rc6-l56; KDE/4.10.5; x86_64; ; )
In-Reply-To: <3e4b87d7be693579f25a8885c96c2b35@hamnavoe.com>
References: <3e4b87d7be693579f25a8885c96c2b35@hamnavoe.com>
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Subject: Re: [9fans] 9P on FPGA?
Topicbox-Message-UUID: b1e51496-ead8-11e9-9d60-3106f5b1d025

On Friday 10 of January 2014 12:25:24 Richard Miller wrote:
> Technically yes, because inferno runs hosted on microCOS on a Nios2 s=
oft cpu
> on Altera FPGAs.  But I imagine you're looking for something lower le=
vel?

thanks, will look into that.
but i imagine this particular implementation may be somewhat coupled to=
=20
inferno and/or Nios.


> But I imagine you're looking for something lower level?

anything goes, Verilog preferred. i'm simply trying to learn something =
new :^)


--=20
dexen deVries

[[[=E2=86=93][=E2=86=92]]]