From mboxrd@z Thu Jan 1 00:00:00 1970 To: 9fans@cse.psu.edu From: "Douglas A. Gwyn" Message-ID: <3B4F350B.EDDD098C@null.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit References: <20010713091130.B8A0D199C0@mail.cse.psu.edu>, <20010713182020.C22003@cackle.proxima.alt.za> Subject: Re: [9fans] how people learn things (was architectures) Date: Mon, 16 Jul 2001 08:54:21 +0000 Topicbox-Message-UUID: ceaa6c8e-eac9-11e9-9e20-41e7f4b1d025 Lucio De Re wrote: > Do you mean to tell me that DEC had a segmented architecture, with > haphazard default "base" registers, a LOCK instruction to lock the > bus for the following fetch cycle (whatever for? even the Univac > 1106 had the more sane test-and-set) and a faulty MOV SS,XX that > did _not_ lock the bus for the following MOV SP,YY as was the > intention? The PDP-11 had a segmented architecture in the sense that there were 8 8KB "pages" in the (D or I) 16-bit address space, each mapped by an 18-bit offset (constrained modulo 64 as I recall) by a register in the Memory Mapping Unit. Later PDP-11s added a second level of memory management to implement 22 bits of real address space. Addresses in opcodes were (at most) 16 bits. In "kernel mode" (the equivalent of a PC's "real mode"), such as under the RT-11 SJ monitor, a user program could load the mapping registers directly whenever it wanted (although doing it stupidly would just cause a crash). I took advantage of that for the PEAC system (no relation to PEAK-11) in order to access the VS60's display list from Fortran programs. A compiler certainly could have generated code that did something similar to make use of the full 18-bit address space within "typical" programs, although to my knowledge no PDP-11 compiler actually did that. (On UNIX, there were a couple of implementations of I-space overlays that mapped instruction code into the 16-bit space as required; I did the compiler/linker piece of that for BRL/JHU PDP-11 UNIX, and as I recall Ron Natalie did the kernel piece. Berkeley did something similar at the same time, but my "thunks" were smaller and faster.) MOV R0,(R0)+ was implemented incorrectly on the PDP-11/20, and the spec for the ISA had to be changed to reflect that. Later models got other things wrong; programs could in fact tell models apart by their semantics for execution of particular code sequences. PDP-11s were designed without thought being given to test-and-set. The first several models of PDP-11 could have interlocking done via INC and ASRB instructions; why this worked is a long story. We could go on, but this is getting far afield. The point is that it isn't just Intel; every computer architecture and implementation has defects. I will say that we took a great step backward when chip manufacturers took over architectural design. It seems that every "generation", people reinvent things without taking into account lessons learned from the previous cycle.