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From: northern snowfall <dbailey27@ameritech.net>
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To: 9fans@cse.psu.edu
Subject: Re: [9fans] Rub your feet on the carpet!
References: <3F7B462F.10203@ameritech.net> <3F7B8C11.6090503@Princeton.EDU>
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Date: Wed,  1 Oct 2003 23:33:10 -0500
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> Wouldn't a SPARC architecture manual suffice? (Mine's at work so I
> can't check to see if it contains anything specific about the device
> in question...)

Yes and no. The SPARC architecture defines the generic rules
for designing a SPARCv8 implementation, but does leave much up
to the designer. For example:

    + MMU implementation can be either the SPARC reference MMU
      or an implementation of the designer's choice. The capability
      of the MMU has a huge impact on the design of supervisor code,
      obviously.

    + Ancillary registers for implementation specific functionality
      are left up to the designer as to use

    + much Coprocessor/FPU functionality is implementation dependent.
      The MB86903 has an onboard FPU, but I have no details on its
      specific capability.

There are other important facets that are implementation specific
and not bound to choices defined in the manual. Of course, the
general functionality of this SPARC CPU is v8 compatible. However,
I'd love to know what else the item is capable of. For example, the
IPX that were shipped with the Weitek CPU have an AT&T MMU on the
board. My IPX seem to have an LSI chip where the AT&T MMU should
be. I'm assuming this means the LSI WK34430P is the MMU, but I don't
know for sure. Google isn't pulling any info.

Also, this CPU is SPARCv7, which makes me even more interested in
specifics.

Don

http://www.7f.no-ip.com/~north_

Debug period.