From mboxrd@z Thu Jan 1 00:00:00 1970 Message-ID: <3e1162e60710081134n2cc1fc71j68236157a6edd427@mail.gmail.com> Date: Mon, 8 Oct 2007 11:34:33 -0700 From: "David Leimbach" To: "Fans of the OS Plan 9 from Bell Labs" <9fans@cse.psu.edu> Subject: Re: [9fans] Re: what about microkernel? In-Reply-To: MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_25544_15749846.1191868473546" References: <283f5df10710080620x5a5ec548pa530b38df41833ab@mail.gmail.com> <546ad2649cbc93791073f5b40499e60e@coraid.com> Topicbox-Message-UUID: cd1a6366-ead2-11e9-9d60-3106f5b1d025 ------=_Part_25544_15749846.1191868473546 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline On 10/8/07, Eric Van Hensbergen wrote: > > On 10/8/07, erik quanstrom wrote: > > > His original Kernel, L3, was written in pure assembly for x86, using > every > > > trick possible. > > > > > > > there's nothing wrong with assembly per ce, but i don't follow this > logic. > > generally speaking, compilers are better than humans at doing > instruction > > scrabble. > > Depends on the compiler ;) > > Ignoring the C++ (or all-assembly) nonsense, the general point of > L3/L4 seemed to be "do IPC really, really well on whatever platform we > are running on and then build a microkernel around it". That's an > oversimplification, and perhaps at that level of abstraction -- that > was the goal of every microkernel (its just many/any didn't succeed at > that goal). Yep, L4 has a high level and low level spec for different architectures. I think there's like up to 255 virtual registers, which I think can actually be realized in real hardware on the Itanium port. IPC is just register swapping then. IPC is also synchronous only. I've been thinking a lot about this, particularly as we've been diving > deep into tracing performance of our network paths as part of the Blue > Gene work. As of our preliminary results, it would seem that Plan 9 > attempts to take the most general approach to things with an emphasis > on keeping everything simple. Unfortunately we end up paying a heavy > price in raw performance (at least in the networking case). It may > well be that "benchmark" performance is irrelevant, but I think its at > least worth reviewing other-OS research from the last 20 years to see > what we can learn. It may be the case that we have cut our > abstractions too high to take advantage of some architectural features > present in modern microprocessors -- it may be that we want to allow > for optimized locking and IPC/queues on particular architectures. > > I've heard mention the idea of turning the Plan 9 kernel into a a pure > 9p mux and building the system around that -- one wonders how > different we would look from a microkernel environment like L4 then. > I know the Japanese folks talked about their efforts of "porting" Plan > 9 on top of L4 at last years IWP9 -- I wonder if they've made any > further progress... I'd be very curious to know how that went... -eric > ------=_Part_25544_15749846.1191868473546 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline

On 10/8/07, Eric Van Hensbergen <ericvh@gmail.com> wrote:
On 10/8/07, erik quanstrom <quanstro@coraid.com> wrote:
> > His original Kernel, L3, was written in pure assembly for x86, using every
> > trick possible.
> >
>
> there's nothing wrong with assembly per ce, but i don't follow this logic.
> generally speaking, compilers are better than humans at doing instruction
> scrabble.

Depends on the compiler ;)

Ignoring the C++ (or all-assembly) nonsense, the general point of
L3/L4 seemed to be "do IPC really, really well on whatever platform we
are running on and then build a microkernel around it".  That's an
oversimplification, and perhaps at that level of abstraction -- that
was the goal of every microkernel (its just many/any didn't succeed at
that goal).

Yep, L4 has a high level and low level spec for different architectures.  I think there's like up to 255 virtual registers, which I think can actually be realized in real hardware on the Itanium port.

IPC is just register swapping then.  IPC is also synchronous only.

I've been thinking a lot about this, particularly as we've been diving
deep into tracing performance of our network paths as part of the Blue
Gene work.  As of our preliminary results, it would seem that Plan 9
attempts to take the most general approach to things with an emphasis
on keeping everything simple.  Unfortunately we end up paying a heavy
price in raw performance (at least in the networking case).  It may
well be that "benchmark" performance is irrelevant, but I think its at
least worth reviewing other-OS research from the last 20 years to see
what we can learn.  It may be the case that we have cut our
abstractions too high to take advantage of some architectural features
present in modern microprocessors -- it may be that we want to allow
for optimized locking and IPC/queues on particular architectures.

I've heard mention the idea of turning the Plan 9 kernel into a a pure
9p mux and building the system around that -- one wonders how
different we would look from a microkernel environment like L4 then.
I know the Japanese folks talked about their efforts of "porting" Plan
9 on top of L4 at last years IWP9 -- I wonder if they've made any
further progress...

I'd be very curious to know how that went...

 

        -eric

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