From mboxrd@z Thu Jan  1 00:00:00 1970
Message-ID: <44A3EB7A.708@lanl.gov>
Date: Thu, 29 Jun 2006 09:02:18 -0600
From: Ronald G Minnich <rminnich@lanl.gov>
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To: Fans of the OS Plan 9 from Bell Labs <9fans@cse.psu.edu>
Subject: Re: [9fans] usb keyboard and mouse?
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	<20060629115531.GB5893@augusta.math.psu.edu>
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Dan Cross wrote:
> On Wed, Jun 28, 2006 at 10:31:26PM -0700, Mike Haertel wrote:
> 
>>The implementation is chipset dependent.  Often what happens is
>>that the chipset recognizes an I/O request to port 0x60 or 0x64 and
>>aborts the request with an SMI (system management interrupt).  This
>>is a *very* non-maskable interrupt (more non-maskable than NMI...)
>>that causes the processor to save pretty much all its register state
>>in a special memory area, and jump to a handler in the system BIOS.
>>The BIOS SMI handler examines the saved register state, figures out
>>what the OS was trying to do, runs a software model of the PS/2
>>keyboard controller's state, chats with the USB keyboard, formulates
>>an appropriate response, emulates the I/O instruction the OS was
>>trying to do, and resumes execution of the OS at the instruction
>>following the I/O instruction.
>>
>>Some chipsets might do it directly in hardware rather than using
>>the SMI+BIOS strategy.
> 
> 
> Dear Lord!  At what point is a chicken sacrificed in this process?
> 
> 	- Dan C.
> 

well, it does get better. On the GX2, the BIOS is a message-passing 
microkernel that lives in SMI. I am not making this up.

ron