[9fans] ARM instruction

[9fans] ARM instruction

[Ronald G. Minnich]

anybody know what MOVW.P is in 5a?

ron

Re: [9fans] ARM instruction

[Bruce Ellis]

the .P sets the PFLAG which "indicates that each address
in the range is incremented ... before it is used to access memory".

Froggie rulez.

brucee

On Thu, 10 Mar 2005 10:46:33 -0700 (MST), Ronald G. Minnich
<rminnich@lanl.gov> wrote:
>
> anybody know what MOVW.P is in 5a?
>
> ron

Re: [9fans] ARM instruction

[Ronald G. Minnich]

On Fri, 11 Mar 2005, Bruce Ellis wrote:

> the .P sets the PFLAG which "indicates that each address
> in the range is incremented ... before it is used to access memory".

well then that worries me more.

I'm seeing a usage from 5c that is like this:

	MOVW	$16384, R3
	MOVE	$1038, R2
	MOVW.P	R2, 4(R3)

the problem is that it shouldn't be 4(R3), it should be 0(R3). And the
pre-increment only makes it worse. I can't quite figure out what 5c is
doing here.

any ARM guys left out there?

ron

Re: [9fans] ARM instruction

[Charles Forsyth]

	MOVW	$1, R2
	MOVW.P	R2, $4(R3)

in the handbook P=0 is post-index and P=1 is pre-index,
but the 5? combination uses .P to mean `post index'
that
	MOVW	4(R5), ...
does what it does everywhere else.

thus .P is the relatively rare post-index, not `set the P bit'.
but with post-indexing, the hardware also automatically
writes back the post-indexed value to the base register
(``the write bit is redundant''), so the effect is to help
to step through memory (as in /sys/src/9/bitsy/l.s cacheflush).

the strange thing is, though, that i can't provoke that
code sequence with a simple variant of the example posted.
i know it's possible, because i've seen it.