From mboxrd@z Thu Jan  1 00:00:00 1970
Message-ID: <464e0390ad0632372b73a295a0b41ce4@terzarima.net>
From: Charles Forsyth <forsyth@terzarima.net>
Date: Thu, 10 Mar 2005 20:14:07 +0000
To: 9fans@cse.psu.edu
Subject: Re: [9fans] ARM instruction
In-Reply-To: <Pine.LNX.4.58.0503101122060.12217@enigma.lanl.gov>
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	MOVW	$1, R2
	MOVW.P	R2, $4(R3)

in the handbook P=0 is post-index and P=1 is pre-index,
but the 5? combination uses .P to mean `post index'
that
	MOVW	4(R5), ...
does what it does everywhere else.

thus .P is the relatively rare post-index, not `set the P bit'.
but with post-indexing, the hardware also automatically
writes back the post-indexed value to the base register
(``the write bit is redundant''), so the effect is to help
to step through memory (as in /sys/src/9/bitsy/l.s cacheflush).

the strange thing is, though, that i can't provoke that
code sequence with a simple variant of the example posted.
i know it's possible, because i've seen it.