From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris McGee Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 (1.0) Date: Thu, 6 Sep 2018 17:21:09 -0400 Message-Id: <9205E070-EAD3-40A5-9F06-92DCF217BB98@gmail.com> References: In-Reply-To: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Subject: Re: [9fans] Is Plan 9 C "Less Dangerous?" Topicbox-Message-UUID: e2b9b77e-ead9-11e9-9d60-3106f5b1d025 Thanks Richard, This looks like it fits the bill: open, small, simple. How was it formally v= erified? This doesn=E2=80=99t seem to need any of the chisel/scala suff, which is gre= at. How can I help with the compiler port? Which fpga board do you recommend? Chris On Sep 6, 2018, at 1:48 PM, Richard Miller <9fans@hamnavoe.com> wrote: >> It could be, but after having looked briefly at the size of the design fo= r >> RISC-V Rocket and especially BOOM I wonder if it's all overly complicated= . >> They even built their own high level hardware language (Chisel) that >> generates Verilog using Scala. Yuck. >=20 > It's possible to build a simple and perfectly usable RISC-V processor > on an FPGA in verilog. The one I use is > https://github.com/cliffordwolf/picorv32 , written by Clifford Wolf. > Its small size means it can be (and has been) formally verified, and > (for some applications at least) you can compensate for the modest > performance by putting lots of them on one chip. >=20 >> Also, there's appears to be quite alot of compiler optimizations in gcc f= or >> RISC-based chips. >=20 > Again, it's possible to build a simple and perfectly usable C compiler > for RISC-V without going overboard with optimisation. I've been > working on re-targeting the Plan 9 C toolchain for RISC-V. It's at > the stage where it can successfully compile itself, but floating point > support is not yet complete. If anyone is interested, let me know. >=20