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* [9fans] risc-v port progress at IWP9
@ 2025-05-29 20:35 Ron Minnich
  2025-05-29 21:35 ` Charles Forsyth
  0 siblings, 1 reply; 5+ messages in thread
From: Ron Minnich @ 2025-05-29 20:35 UTC (permalink / raw)
  To: 9fans

Daniel and Shawn made good progress on the risc-v port, and their
experience reminded me of a standard test I used to use while doing
ports.

long story short, for blue gene and other ports (early amd64) we added
this test in main

ulong x = 0x12345678;

main()
{
    if (x != 0x12345678) panic("unaligned data"):

...


how can this test fail? x is in the data segment, but the immediate in
the test is in the text segment. This test is a quick and easy way to
check if your data segment is correctly loaded in memory.

In some ports, the data is aligned by code in l.s that moves it.

There are some really nasty, confusing errors that will arise in a
seemingly working kernel if data is not aligned.

I always add this test when I'm doing a port. It catches a problem
that is otherwise very confusing, and presents as strings  not set up
right, variables wrong, etc.

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2025-06-06  0:48       ` [9fans] risc-v port progress at IWP9 Romano
2025-06-06  7:44       ` Maht Lawless via 9fans
2025-05-29 20:35 Ron Minnich
2025-05-29 21:35 ` Charles Forsyth
2025-05-29 21:55   ` Charles Forsyth

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