Re: [9fans] dumb kw question

[erik quanstrom <quanstro@quanstro.net>]

> if Descralign is 16, and sizeof(Rx) is 16, but the cache line size is 32,
> i'm surprised it works. there are two descriptors per cache line,
> and two processors, but only one sees both caches. the other processor -
> the ethernet controller - depending how it's wired up,
> sees at best L2 but more usually uncached RAM. i don't see how this cache
> flushing (and invalidation elsewhere) can give a coherent view of both descriptors.
>
> i'd expect to see peculiar errors, such as non-trivial levels of retransmission
> (both sides) causing poor performance.

that was the sort of confusion i was expecting to ensue.
i suppose the proper course of action would be to only
fill out full cache lines.  the myricom hardware demands
this sort of treatment.  but at the very least, it will require
half as many l2 flushes.

however, there's only one rx kproc to be scheduled.  could that
alliviate your concerns?  i'm very fuzzy on arm caching.
for instance, when will the l2 sync up with main memory,
without being manually flushed?

- erik