From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bakul Shah Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.11\)) Date: Fri, 9 Aug 2019 15:51:22 -0700 References: <40745EA5-3815-4E4F-9FE0-8F83697E74BA@bitblocks.com> To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> In-Reply-To: Message-Id: Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs Topicbox-Message-UUID: 03fa245a-eada-11e9-9d60-3106f5b1d025 On Aug 9, 2019, at 2:34 PM, Charles Forsyth = wrote: >=20 > Since the resources are small if not tiny, a little systems analysis = and design is probably needed, but it looks like a bit of fun, until the = inevitable moment of "why am I here?". >=20 > On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth = wrote: > The device I've got is ESP32-WROOM-32. None of the boards I've seen = that use it bother with external memory, > so memory is limited, especially the way it's partitioned. >=20 > On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth = wrote: > The ESP32 has got several MMUs. The characteristics are different = depending on the part that a given MMU accesses (flash, ROM, SRAM, = external memory). > Some things are accessed using Memory Protection Units instead, which = control access by Process ID, but don't do mapping. Others including = some of the SRAMs are accessed through > an MMU that can do virtual to physical mapping. The MMUs for internal = SRAM0 and 2 choose protection for a given physical page as none, one or = all of PIDs 2 to 7, with the virtual address that > maps to it. PIDs 0 and 1 can access everything. PID 0 can execute = privileged instructions. > A large chunk of SRAM (SRAM 1) has only Memory Protection and no = translation. The external memory MMU is the most general (most = conventional). Thanks. Not ideal for plan9 but it would be nice to have access to all its IO = capabilities over 9p.=