From: Paul Lalonde <plalonde@telus.net>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
Subject: Re: [9fans] image/memimage speed
Date: Fri, 5 Dec 2008 21:52:59 -0800 [thread overview]
Message-ID: <C2553F35-52CA-47F9-B506-C79AAC3D3151@telus.net> (raw)
In-Reply-To: <13426df10812051211r3ddc047cg8fade7f581d3efe8@mail.gmail.com>
I'll try to track down an actual PCIe card rather than a simulator and
run down some numbers on Monday.
Paul
On 5-Dec-08, at 12:11 PM, ron minnich wrote:
>
> On Fri, Dec 5, 2008 at 11:30 AM, Paul Lalonde <plalonde@telus.net>
> wrote:
>> But random access patterns suck at being speculatively cached.
>> Linear access patterns still require reasonably careful work for
>> the caching
>> to do the right thing.
>> Expecting your entire frame buffer to be cached in L2 isn't
>> particularly
>> reasonable.
>>
>
> I'm pretty sure we can put some #s on this discussion. It's too
> fuzzy for me.
>
> Forget speculative reads, for now. Paul, what kind of time are you
> seeing on your measurements to load a cache line over pcie from a
> card?
>
> ron
>
next prev parent reply other threads:[~2008-12-06 5:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-11-30 22:00 Iruata Souza
2008-11-30 23:54 ` Iruata Souza
2008-12-01 1:29 ` erik quanstrom
2008-12-01 1:54 ` andrey mirtchovski
2008-12-01 2:35 ` erik quanstrom
2008-12-01 3:30 ` andrey mirtchovski
2008-12-01 6:41 ` Paul Lalonde
2008-12-01 14:19 ` Steve Simon
2008-12-01 14:33 ` erik quanstrom
2008-12-05 6:39 ` ron minnich
2008-12-05 13:35 ` erik quanstrom
2008-12-05 18:27 ` Russ Cox
2008-12-05 18:32 ` Russ Cox
2008-12-05 18:49 ` ron minnich
2008-12-05 19:21 ` Paul Lalonde
2008-12-05 19:25 ` erik quanstrom
2008-12-05 19:30 ` Paul Lalonde
2008-12-05 19:40 ` erik quanstrom
2008-12-05 20:11 ` ron minnich
2008-12-06 5:52 ` Paul Lalonde [this message]
2008-12-07 17:00 ` Aki Nyrhinen
2008-12-07 23:22 ` erik quanstrom
2008-12-08 0:17 ` Aki Nyrhinen
2008-12-01 15:24 plalonde
2008-12-05 5:22 ` sqweek
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