From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: In-Reply-To: From: =?UTF-8?Q?Iruat=C3=A3_Souza?= Date: Wed, 5 Sep 2018 08:38:35 -0700 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [9fans] Is Plan 9 C "Less Dangerous?" Topicbox-Message-UUID: e12a558a-ead9-11e9-9d60-3106f5b1d025 On Wed, Sep 5, 2018 at 4:45 AM Chris McGee wrote: > > >> Wasn't that the whole point of RISC? > > > It could be, but after having looked briefly at the size of the design fo= r RISC-V Rocket and especially BOOM I wonder if it's all overly complicated= . They even built their own high level hardware language (Chisel) that gene= rates Verilog using Scala. Yuck. > > Also, there's appears to be quite alot of compiler optimizations in gcc f= or RISC-based chips. > > Could you get away with a much simpler, smaller hardware design and still= run Plan 9 in a reasonable way? Maybe one side of the software/hardware di= vide has to take on more complexity to help simplify the other side? Take a look at greenarraychips.com and how Chuck Moore tries to simplify the whole instead of software or hardware.