From: cherry <lunaria21@gmail.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
Subject: Re: [9fans] MIPS LE fp register ordering in MOVD
Date: Thu, 26 Dec 2013 22:41:00 -0500 [thread overview]
Message-ID: <CACzOosDxFnO2v+iHQ1ZxrkZh8oHwVEoOuQc_qDVH7Cx5dm5gAA@mail.gmail.com> (raw)
In-Reply-To: <CACzOosASeD5Nf8wW54T_KEF6pudeDsxPOKxfO0Mp8fZdzC7fDw@mail.gmail.com>
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On Thu, Dec 26, 2013 at 6:46 PM, cherry <lunaria21@gmail.com> wrote:
> Another issue is 0l/vl seems to output wrong bits for single precision
> floats in little endian mode, due to a similar reason: it used bytes 4-7
> instead of 0-3. This seems to fix it:
>
> % diff /sys/src/cmd/vl/asm.c asm.c
> 672c672,675
> < buf.dbuf[l] = cast[fnuxi8[i+4]];
> ---
> > if(little)
> > buf.dbuf[l] = cast[fnuxi8[i]];
> > else
> > buf.dbuf[l] = cast[fnuxi8[i+4]];
>
> An alternative fix would be simply use fnuxi4 instead of fnuxi8, so that
> both BE and LE would work (I guess, don't have BE machine to test).
>
Indeed I can test it, simply diff the output of vl before and after. Using,
fnuxi4 does NOT work for BE, as fnuxi4 is only set for LE
(obj.c:1385,1404), probably due to (the same or another) historical reason.
- cherry
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next prev parent reply other threads:[~2013-12-27 3:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-24 17:20 cherry
2013-12-26 23:46 ` cherry
2013-12-26 23:48 ` erik quanstrom
2013-12-27 0:25 ` cherry
2013-12-27 1:40 ` cinap_lenrek
2013-12-27 3:40 ` cherry
2013-12-30 7:12 ` Skip Tavakkolian
2013-12-27 3:41 ` cherry [this message]
2013-12-27 4:32 ` Bruce Ellis
2013-12-27 4:41 ` lucio
2013-12-27 22:32 ` Bruce Ellis
2013-12-28 1:22 ` cherry
2013-12-28 1:47 ` Bruce Ellis
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