From mboxrd@z Thu Jan  1 00:00:00 1970
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References: <CAHL7psFg6JgatGw3hQb93kpkrZFGq7vtcz7eMkWWbM0cNfMGzA@mail.gmail.com>
Date: Tue,  2 Feb 2016 10:42:03 -0600
Message-ID: <CAGGHmKFWKzep+c5yuDuJEBVSf+US_Ck9AQSeUt3AJ7W-ODfTrw@mail.gmail.com>
From: Steven Stallion <sstallion@gmail.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
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Subject: Re: [9fans] FP register usage in Plan9 assembler
Topicbox-Message-UUID: 81c5c6d8-ead9-11e9-9d60-3106f5b1d025

Hi Giacomo,

It's probably worth mentioning that learning assembly using the Plan 9
assembler is probably a bad idea. *a makes heavy use of pseudo
instructions and registers and unless you're well versed in its
quirks, can be very confusing when looking at more common assembly
dialects. Many instructions are directly encoded in the instruction
stream, largely due to the fact that it is more difficult than it
should be to extend the assembler as architectures evolve*. More
mechanically, Plan 9 makes use of a loader, which causes a number of
operations you would expect to be present in the assembler to be
deferred until later.

None of this is intended to dissuade of course, but as always in Plan
9: caveat emptor.

If you haven't looked already, a good place to start is /sys/doc/asm.ms.

Cheers,

Steve

* The diff to update support for ARMv7-A to 5a came in at over 2800
lines; this was to add a handful of instructions.

On Mon, Feb 1, 2016 at 10:47 AM, Giacomo Tesio <giacomo@tesio.it> wrote:
> I'm studying the 9front's amd64 kernel, and I'm pretty new to assembler
> programming, so sorry if my question is too dumb...
>
> I cannot understand the FP pseudo register usage.
> The cpuid function, for example, is implemented as
>
> /*
>  * The CPUID instruction is always supported on the amd64.
>  */
> TEXT cpuid(SB), $-4
>     MOVL    RARG, AX            /* function in AX */
>     CPUID
>
>     MOVQ    info+8(FP), BP
>     MOVL    AX, 0(BP)
>     MOVL    BX, 4(BP)
>     MOVL    CX, 8(BP)
>     MOVL    DX, 12(BP)
>     RET
>
> What I miss is where "info" comes from. I cannot
>
> Apparently the GAS equivalent is:
>
> .align 4
> .globl cpuid
> cpuid:
>     mov    %ebp,%eax
>     cpuid
>     mov    0x10(%rsp),%rbp
>     mov    %eax,0x0(%rbp)
>     mov    %ebx,0x4(%rbp)
>     mov    %ecx,0x8(%rbp)
>     mov    %edx,0xc(%rbp)
>     retq
>
> Thus apparently info+8(FP) becomes 0x10(%rsp)
> Why? I know that FP is a pseudo register, but shouldn't it be different from
> SP?
>
> And why info's value is 8? Is it the pointer size?
>
> Another example:
>
> TEXT insb(SB), 1, $-4
>     MOVL    RARG, DX            /* MOVL    port+0(FP), DX */
>     MOVQ    address+8(FP), DI
>     MOVL    count+16(FP), CX
>     CLD
>     REP;    INSB
>     RET
>
> should be equivalent to
>
> .align 4
> .globl insb
> insb:
>     mov    %ebp,%edx
>     mov    0x10(%rsp),%rdi
>     mov    0x18(%rsp),%ecx
>     cld
>     rep insb
>     retq
>
> Again I cannot find a definition of address and count, but both seem to be
> be valued as 8, why?
>
>
> Giacomo
>