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From: Lucio De Re <lucio.dere@gmail.com>
Date: Wed,  7 Aug 2019 10:07:32 +0200
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To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
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Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs
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On 8/7/19, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> I've not previously seen an architecture where so many cache and TLB
> control instructions were in the primary space and took up so much of it.
>
I guess the remainder is RISC :-).

Lucio.