Re: [9fans] Is Plan 9 C "Less Dangerous?"

[Skip Tavakkolian <skip.tavakkolian@gmail.com>]

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Thank you.  This is fantastic.

I've been looking into running Plan 9 in JSLinux (
https://bellard.org/jslinux/  and https://bellard.org/jslinux/tech.html)
and came across riscvemu (https://bellard.org/riscvemu/). I wonder if it
might be a useful for trying things on.

On Thu, Sep 6, 2018 at 10:48 AM Richard Miller <9fans@hamnavoe.com> wrote:

> > It could be, but after having looked briefly at the size of the design
> for
> > RISC-V Rocket and especially BOOM I wonder if it's all overly
> complicated.
> > They even built their own high level hardware language (Chisel) that
> > generates Verilog using Scala. Yuck.
>
> It's possible to build a simple and perfectly usable RISC-V processor
> on an FPGA in verilog.  The one I use is
> https://github.com/cliffordwolf/picorv32 , written by Clifford Wolf.
> Its small size means it can be (and has been) formally verified, and
> (for some applications at least) you can compensate for the modest
> performance by putting lots of them on one chip.
>
> > Also, there's appears to be quite alot of compiler optimizations in gcc
> for
> > RISC-based chips.
>
> Again, it's possible to build a simple and perfectly usable C compiler
> for RISC-V without going overboard with optimisation.  I've been
> working on re-targeting the Plan 9 C toolchain for RISC-V.  It's at
> the stage where it can successfully compile itself, but floating point
> support is not yet complete.  If anyone is interested, let me know.
>
>

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