From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: In-Reply-To: From: Skip Tavakkolian Date: Thu, 6 Sep 2018 12:08:55 -0700 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: multipart/alternative; boundary="0000000000000d8cb3057538a088" Subject: Re: [9fans] Is Plan 9 C "Less Dangerous?" Topicbox-Message-UUID: e2a975c6-ead9-11e9-9d60-3106f5b1d025 --0000000000000d8cb3057538a088 Content-Type: text/plain; charset="UTF-8" Thank you. This is fantastic. I've been looking into running Plan 9 in JSLinux ( https://bellard.org/jslinux/ and https://bellard.org/jslinux/tech.html) and came across riscvemu (https://bellard.org/riscvemu/). I wonder if it might be a useful for trying things on. On Thu, Sep 6, 2018 at 10:48 AM Richard Miller <9fans@hamnavoe.com> wrote: > > It could be, but after having looked briefly at the size of the design > for > > RISC-V Rocket and especially BOOM I wonder if it's all overly > complicated. > > They even built their own high level hardware language (Chisel) that > > generates Verilog using Scala. Yuck. > > It's possible to build a simple and perfectly usable RISC-V processor > on an FPGA in verilog. The one I use is > https://github.com/cliffordwolf/picorv32 , written by Clifford Wolf. > Its small size means it can be (and has been) formally verified, and > (for some applications at least) you can compensate for the modest > performance by putting lots of them on one chip. > > > Also, there's appears to be quite alot of compiler optimizations in gcc > for > > RISC-based chips. > > Again, it's possible to build a simple and perfectly usable C compiler > for RISC-V without going overboard with optimisation. I've been > working on re-targeting the Plan 9 C toolchain for RISC-V. It's at > the stage where it can successfully compile itself, but floating point > support is not yet complete. If anyone is interested, let me know. > > --0000000000000d8cb3057538a088 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thank you.=C2=A0 This is fantastic.

I&#= 39;ve been looking into running Plan 9 in JSLinux (https://bellard.org/jslinux/=C2=A0 and=C2=A0https://bellard.org/jslinux/tech.ht= ml) and came across riscvemu (https://bellard.org/riscvemu/). I wonder if it might be a useful for t= rying things on.

On Thu, Sep 6, 2018 at 10:48 AM Richard Miller <9fans@hamnavoe.com> wrote:
<= /div>
> It could be, but after having look= ed briefly at the size of the design for
> RISC-V Rocket and especially BOOM I wonder if it's all overly comp= licated.
> They even built their own high level hardware language (Chisel) that > generates Verilog using Scala. Yuck.

It's possible to build a simple and perfectly usable RISC-V processor on an FPGA in verilog.=C2=A0 The one I use is
https://github.com/cliffordwolf/picorv32 , written by Cl= ifford Wolf.
Its small size means it can be (and has been) formally verified, and
(for some applications at least) you can compensate for the modest
performance by putting lots of them on one chip.

> Also, there's appears to be quite alot of compiler optimizations i= n gcc for
> RISC-based chips.

Again, it's possible to build a simple and perfectly usable C compiler<= br> for RISC-V without going overboard with optimisation.=C2=A0 I've been working on re-targeting the Plan 9 C toolchain for RISC-V.=C2=A0 It's a= t
the stage where it can successfully compile itself, but floating point
support is not yet complete.=C2=A0 If anyone is interested, let me know.
--0000000000000d8cb3057538a088--