From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: <40745EA5-3815-4E4F-9FE0-8F83697E74BA@bitblocks.com> In-Reply-To: From: Skip Tavakkolian Date: Fri, 9 Aug 2019 15:53:59 -0700 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: multipart/alternative; boundary="0000000000006ed7bd058fb70d7f" Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs Topicbox-Message-UUID: 04010518-eada-11e9-9d60-3106f5b1d025 --0000000000006ed7bd058fb70d7f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable I'm not sure if the effort would be worth it; but if you add support for esp32, I think it would be better for the os to be something like the one you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9. Staying with FreeRTOS would need removal of GCC specific things from OS and dealing with lots of drivers in C++. The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem more appropriate for an "embedded" Plan 9. (*) for those who have not seen it, it is here: % ls -l /n/sources/contrib/forsyth/avr* --rw-rw-r-- M 518 bootes sys 251227 Sep 4 2011 /n/sources/contrib/forsyth/avr.9gz On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth wrote: > Since the resources are small if not tiny, a little systems analysis and > design is probably needed, but it looks like a bit of fun, until the > inevitable moment of "why am I here?". > > On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth > wrote: > >> The device I've got is ESP32-WROOM-32. None of the boards I've seen that >> use it bother with external memory, >> so memory is limited, especially the way it's partitioned. >> >> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth >> wrote: >> >>> The ESP32 has got several MMUs. The characteristics are different >>> depending on the part that a given MMU accesses (flash, ROM, SRAM, exte= rnal >>> memory). >>> Some things are accessed using Memory Protection Units instead, which >>> control access by Process ID, but don't do mapping. Others including so= me >>> of the SRAMs are accessed through >>> an MMU that can do virtual to physical mapping. The MMUs for internal >>> SRAM0 and 2 choose protection for a given physical page as none, one or= all >>> of PIDs 2 to 7, with the virtual address that >>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute >>> privileged instructions. >>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no >>> translation. The external memory MMU is the most general (most >>> conventional). >>> >>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah wrote: >>> >>>> esp32 doesn=E2=80=99t have an mmu, right? >>>> >>>> On Jul 26, 2019, at 03:30, Charles Forsyth >>>> wrote: >>>> >>>> I was thinking of doing that since I've got an ESP-32 for some reason >>>> >>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic >>>> wrote: >>>> >>>>> I was reading the post Why Didn't Plan 9 Succeed >>>>> on Hacker News. >>>>> >>>>> Made me think that Plan 9 for IoT system of systems could be viable. >>>>> >>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is >>>>> there a Plan 9 C compiler for Xtensa ISA CPUs? >>>>> >>>>> --0000000000006ed7bd058fb70d7f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
I'm not sure if the effort would be worth it; but if y= ou add support for esp32, I think it would be better for the os to be somet= hing like the one you had in kencc for AVR (*) or possibly Russ' libtas= k, rather than Plan 9. Staying with FreeRTOS would need removal of GCC spec= ific things from OS and dealing with lots of drivers in C++.

<= /div>
The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) s= eem more appropriate for an "embedded" Plan 9.

(*) for those who have not seen it, it is here:
% ls -l /n= /sources/contrib/forsyth/avr*
--rw-rw-r-- M 518 bootes sys 251227 Sep = =C2=A04 =C2=A02011 /n/sources/contrib/forsyth/avr.9gz

On Fri, Aug 9, 2= 019 at 2:36 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
Since the resources are smal= l if not tiny, a little systems analysis and design is probably needed, but= it looks like a bit of fun, until the inevitable moment of "why am I = here?".

On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.co= m> wrote:
The device I've got is ESP32-WROOM-32. None of the bo= ards I've seen that use it bother with external memory,
so memory i= s limited, especially the way it's partitioned.

On Fri, Aug 9, 201= 9 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
The ESP32 ha= s got several MMUs. The characteristics are different depending on the part= that a given MMU accesses (flash, ROM, SRAM, external memory).
Some th= ings are accessed using Memory Protection Units instead, which control acce= ss by Process ID, but don't do mapping. Others including some of the SR= AMs are accessed through
an MMU that can do virtual to physical m= apping. The MMUs for internal SRAM0 and 2 choose protection for a given phy= sical page as none, one or all of PIDs 2 to 7, with the virtual address tha= t
maps to it. PIDs 0 and 1 can access everything. PID 0 can execu= te privileged instructions.
A large chunk of SRAM (SRAM 1) has on= ly Memory Protection and no translation. The external memory MMU is the mos= t general (most conventional).

On Fri, Aug 9, 2019 at 3:19 PM Bakul Sh= ah <bakul@bitbl= ocks.com> wrote:
esp32 doe= sn=E2=80=99t have an mmu, right?

On Jul 26, 2019,= at 03:30, Charles Forsyth <charles.forsyth@gmail.com> wrote:

I was thinking of= doing that since I've got an ESP-32 for some reason

On Fri, Jul 26, 201= 9 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
I was reading the post=C2= =A0Why Didn't Plan 9 Succeed=C2=A0on Hacker News.

=
Made me think that Plan 9 for IoT system of systems could be viable.

To that end, ESP-32 modules look capable enough to = run Plan 9, but is there a Plan 9 C compiler for Xtensa ISA CPUs?=C2=A0

--0000000000006ed7bd058fb70d7f--