From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: <40745EA5-3815-4E4F-9FE0-8F83697E74BA@bitblocks.com> In-Reply-To: From: Shane Morris Date: Sat, 10 Aug 2019 07:48:08 +1000 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: multipart/alternative; boundary="0000000000001091bf058fb6229f" Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs Topicbox-Message-UUID: 03e42402-eada-11e9-9d60-3106f5b1d025 --0000000000001091bf058fb6229f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Wireless NinePea perhaps? https://github.com/echoline/NinePea On Sat, Aug 10, 2019 at 7:36 AM Charles Forsyth wrote: > Since the resources are small if not tiny, a little systems analysis and > design is probably needed, but it looks like a bit of fun, until the > inevitable moment of "why am I here?". > > On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth > wrote: > >> The device I've got is ESP32-WROOM-32. None of the boards I've seen that >> use it bother with external memory, >> so memory is limited, especially the way it's partitioned. >> >> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth >> wrote: >> >>> The ESP32 has got several MMUs. The characteristics are different >>> depending on the part that a given MMU accesses (flash, ROM, SRAM, exte= rnal >>> memory). >>> Some things are accessed using Memory Protection Units instead, which >>> control access by Process ID, but don't do mapping. Others including so= me >>> of the SRAMs are accessed through >>> an MMU that can do virtual to physical mapping. The MMUs for internal >>> SRAM0 and 2 choose protection for a given physical page as none, one or= all >>> of PIDs 2 to 7, with the virtual address that >>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute >>> privileged instructions. >>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no >>> translation. The external memory MMU is the most general (most >>> conventional). >>> >>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah wrote: >>> >>>> esp32 doesn=E2=80=99t have an mmu, right? >>>> >>>> On Jul 26, 2019, at 03:30, Charles Forsyth >>>> wrote: >>>> >>>> I was thinking of doing that since I've got an ESP-32 for some reason >>>> >>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic >>>> wrote: >>>> >>>>> I was reading the post Why Didn't Plan 9 Succeed >>>>> on Hacker News. >>>>> >>>>> Made me think that Plan 9 for IoT system of systems could be viable. >>>>> >>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is >>>>> there a Plan 9 C compiler for Xtensa ISA CPUs? >>>>> >>>>> --0000000000001091bf058fb6229f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Wireless NinePea perhaps?

https://github.com/echoline/N= inePea

On Sat, Aug 10, 2019 at 7:36 AM Charles Forsyth <charles.forsyth@gmail.com> wro= te:
Since the resources are small if not tiny, a little systems analysis a= nd design is probably needed, but it looks like a bit of fun, until the ine= vitable moment of "why am I here?".

On Fri, Aug 9, 2019 at 4:50 PM= Charles Forsyth <charles.forsyth@gmail.com> wrote:
The device I've got = is ESP32-WROOM-32. None of the boards I've seen that use it bother with= external memory,
so memory is limited, especially the way it's par= titioned.

On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gma= il.com> wrote:
The ESP32 has got several MMUs. The characteristics = are different depending on the part that a given MMU accesses (flash, ROM, = SRAM, external memory).
Some things are accessed using Memory Protectio= n Units instead, which control access by Process ID, but don't do mappi= ng. Others including some of the SRAMs are accessed through
an MM= U that can do virtual to physical mapping. The MMUs for internal SRAM0 and = 2 choose protection for a given physical page as none, one or all of PIDs 2= to 7, with the virtual address that
maps to it. PIDs 0 and 1 can= access everything. PID 0 can execute privileged instructions.
A = large chunk of SRAM (SRAM 1) has only Memory Protection and no translation.= The external memory MMU is the most general (most conventional).

On F= ri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
esp32 doesn=E2=80=99t have an mmu, right?

On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gma= il.com> wrote:

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