From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: In-Reply-To: From: Chris McGee Date: Wed, 5 Sep 2018 07:42:52 -0400 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: multipart/alternative; boundary="000000000000004f6e05751e472a" Subject: Re: [9fans] Is Plan 9 C "Less Dangerous?" Topicbox-Message-UUID: e10eaa24-ead9-11e9-9d60-3106f5b1d025 --000000000000004f6e05751e472a Content-Type: text/plain; charset="UTF-8" > Wasn't that the whole point of RISC? > It could be, but after having looked briefly at the size of the design for RISC-V Rocket and especially BOOM I wonder if it's all overly complicated. They even built their own high level hardware language (Chisel) that generates Verilog using Scala. Yuck. Also, there's appears to be quite alot of compiler optimizations in gcc for RISC-based chips. Could you get away with a much simpler, smaller hardware design and still run Plan 9 in a reasonable way? Maybe one side of the software/hardware divide has to take on more complexity to help simplify the other side? --000000000000004f6e05751e472a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Wasn't that the whol= e point of RISC?

It could be, b= ut after having looked briefly at the size of the design for RISC-V Rocket = and especially BOOM I wonder if it's all overly complicated. They even = built their own high level hardware language (Chisel) that generates Verilo= g using Scala. Yuck.

Also, there's appears to = be quite alot of compiler optimizations in gcc for RISC-based chips.
<= div>
Could you get away with a much simpler, smaller hardware= design and still run Plan 9 in a reasonable way? Maybe one side of the sof= tware/hardware divide has to take on more complexity to help simplify the o= ther side?
--000000000000004f6e05751e472a--