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* [9fans] 9P on FPGA?
@ 2014-01-10 12:13 dexen deVries
  2014-01-10 12:25 ` Richard Miller
  2014-01-10 13:22 ` Charles Forsyth
  0 siblings, 2 replies; 4+ messages in thread
From: dexen deVries @ 2014-01-10 12:13 UTC (permalink / raw)
  To: Fans of the OS Plan 9 from Bell Labs

is there any known 9P implementation for FPGA? or has anyone been working on 
communicating with FPGAs over 9P?


-- 
dexen deVries

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [9fans] 9P on FPGA?
  2014-01-10 12:13 [9fans] 9P on FPGA? dexen deVries
@ 2014-01-10 12:25 ` Richard Miller
  2014-01-10 12:36   ` dexen deVries
  2014-01-10 13:22 ` Charles Forsyth
  1 sibling, 1 reply; 4+ messages in thread
From: Richard Miller @ 2014-01-10 12:25 UTC (permalink / raw)
  To: 9fans

> is there any known 9P implementation for FPGA? or has anyone been working on
> communicating with FPGAs over 9P?

Technically yes, because inferno runs hosted on microCOS on a Nios2 soft cpu on
Altera FPGAs.  But I imagine you're looking for something lower level?




^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [9fans] 9P on FPGA?
  2014-01-10 12:25 ` Richard Miller
@ 2014-01-10 12:36   ` dexen deVries
  0 siblings, 0 replies; 4+ messages in thread
From: dexen deVries @ 2014-01-10 12:36 UTC (permalink / raw)
  To: Fans of the OS Plan 9 from Bell Labs

On Friday 10 of January 2014 12:25:24 Richard Miller wrote:
> Technically yes, because inferno runs hosted on microCOS on a Nios2 soft cpu
> on Altera FPGAs.  But I imagine you're looking for something lower level?

thanks, will look into that.
but i imagine this particular implementation may be somewhat coupled to 
inferno and/or Nios.


> But I imagine you're looking for something lower level?

anything goes, Verilog preferred. i'm simply trying to learn something new :^)


-- 
dexen deVries

[[[↓][→]]]




^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [9fans] 9P on FPGA?
  2014-01-10 12:13 [9fans] 9P on FPGA? dexen deVries
  2014-01-10 12:25 ` Richard Miller
@ 2014-01-10 13:22 ` Charles Forsyth
  1 sibling, 0 replies; 4+ messages in thread
From: Charles Forsyth @ 2014-01-10 13:22 UTC (permalink / raw)
  To: Fans of the OS Plan 9 from Bell Labs

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On 10 January 2014 12:13, dexen deVries <dexen.devries@gmail.com> wrote:

> is there any known 9P implementation for FPGA? or has anyone been working
> on
> communicating with FPGAs over 9P?
>

similar: there was a project at the University of York ("Styx on a Chip")
that developed some sort of module that could allow devices to export name
spaces. Styx and 9P2000 were by that time identical.

ftp://ftp.cs.*york*.ac.uk/papers/rtspapers/R:Audsley:2005a.pdf‎
www.dcs.gla.ac.uk/~marks/*styx*.pdf‎
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.3488&rep=rep1&type=pdf

The earliest project was demonstrated at an Embedded Systems show at
Birmingham NEC.
It was one of only two rather cool things at the show (most of the show was
boring UML stuff).
The other cool thing was Lars Bok's (Esmertec) OSVM: real-time
garbage-collecting Smalltalk running in 64k on a micro, offering on-the-fly
code updates. Superb.

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^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2014-01-10 13:22 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-01-10 12:13 [9fans] 9P on FPGA? dexen deVries
2014-01-10 12:25 ` Richard Miller
2014-01-10 12:36   ` dexen deVries
2014-01-10 13:22 ` Charles Forsyth

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