I've not previously seen an architecture where so many cache and TLB control instructions were in the primary space and took up so much of it.

On Fri, Jul 26, 2019 at 11:30 AM Charles Forsyth <charles.forsyth@gmail.com> wrote:

I was thinking of doing that since I've got an ESP-32 for some reason

On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
I was reading the post Why Didn't Plan 9 Succeed on Hacker News.

Made me think that Plan 9 for IoT system of systems could be viable.

To that end, ESP-32 modules look capable enough to run Plan 9, but is there a Plan 9 C compiler for Xtensa ISA CPUs?