From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 References: <40745EA5-3815-4E4F-9FE0-8F83697E74BA@bitblocks.com> In-Reply-To: From: Charles Forsyth Date: Fri, 9 Aug 2019 16:50:40 +0100 Message-ID: To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net> Content-Type: multipart/alternative; boundary="0000000000008ae112058fb12380" Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs Topicbox-Message-UUID: 03a999ae-eada-11e9-9d60-3106f5b1d025 --0000000000008ae112058fb12380 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The device I've got is ESP32-WROOM-32. None of the boards I've seen that use it bother with external memory, so memory is limited, especially the way it's partitioned. On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth wrote: > The ESP32 has got several MMUs. The characteristics are different > depending on the part that a given MMU accesses (flash, ROM, SRAM, extern= al > memory). > Some things are accessed using Memory Protection Units instead, which > control access by Process ID, but don't do mapping. Others including some > of the SRAMs are accessed through > an MMU that can do virtual to physical mapping. The MMUs for internal > SRAM0 and 2 choose protection for a given physical page as none, one or a= ll > of PIDs 2 to 7, with the virtual address that > maps to it. PIDs 0 and 1 can access everything. PID 0 can execute > privileged instructions. > A large chunk of SRAM (SRAM 1) has only Memory Protection and no > translation. The external memory MMU is the most general (most > conventional). > > On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah wrote: > >> esp32 doesn=E2=80=99t have an mmu, right? >> >> On Jul 26, 2019, at 03:30, Charles Forsyth >> wrote: >> >> I was thinking of doing that since I've got an ESP-32 for some reason >> >> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic wrote= : >> >>> I was reading the post Why Didn't Plan 9 Succeed >>> on Hacker News. >>> >>> Made me think that Plan 9 for IoT system of systems could be viable. >>> >>> To that end, ESP-32 modules look capable enough to run Plan 9, but is >>> there a Plan 9 C compiler for Xtensa ISA CPUs? >>> >>> --0000000000008ae112058fb12380 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
The device I've got is ESP32-WROOM-32. None of the boa= rds I've seen that use it bother with external memory,
so memory is= limited, especially the way it's partitioned.

On Fri, Aug 9, 2019= at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
The ESP32 has got several MMUs.= The characteristics are different depending on the part that a given MMU a= ccesses (flash, ROM, SRAM, external memory).
Some things are accessed u= sing Memory Protection Units instead, which control access by Process ID, b= ut don't do mapping. Others including some of the SRAMs are accessed th= rough
an MMU that can do virtual to physical mapping. The MMUs fo= r internal SRAM0 and 2 choose protection for a given physical page as none,= one or all of PIDs 2 to 7, with the virtual address that
maps to= it. PIDs 0 and 1 can access everything. PID 0 can execute privileged instr= uctions.
A large chunk of SRAM (SRAM 1) has only Memory Protectio= n and no translation. The external memory MMU is the most general (most con= ventional).

On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wr= ote:
esp32 doesn=E2=80=99t have a= n mmu, right?

On Jul 26, 2019, at 03:30, Charles = Forsyth <= charles.forsyth@gmail.com> wrote:

I was thinking of doing that since I= 've got an ESP-32 for some reason

<= div dir=3D"ltr" class=3D"gmail_attr">On Fri, Jul 26, 2019 at 7:38 AM Cyber = Fonic <cyberfo= nic@gmail.com> wrote:
I was reading the post=C2=A0Why Didn't= Plan 9 Succeed=C2=A0on Hacker News.

Made me think t= hat Plan 9 for IoT system of systems could be viable.

<= div>To that end, ESP-32 modules look capable enough to run Plan 9, but is t= here a Plan 9 C compiler for Xtensa ISA CPUs?=C2=A0

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