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Wed, 07 Jan 2026 08:58:33 -0800 (PST) MIME-Version: 1.0 References: <77272bef6ca4f3fd68aa5ce5e96c1981@hamnavoe.com> In-Reply-To: <77272bef6ca4f3fd68aa5ce5e96c1981@hamnavoe.com> From: ron minnich Date: Wed, 7 Jan 2026 08:58:20 -0800 X-Gm-Features: AQt7F2rYnCro4nnFqry4bIVKc5Dl1Nm1Jm8FmJUhRYEf-fg9w0rQZdWZxLraBBI Message-ID: Subject: Re: [9fans] risc-v memory layout To: 9fans <9fans@9fans.net> Content-Type: multipart/alternative; boundary=000000000000cea23a0647cf3371 Topicbox-Policy-Reasoning: moderate: sender is a member; group holds all messages Topicbox-Message-UUID: 1bfd6180-ebea-11f0-a741-a85e10c0285f Archived-At: =?UTF-8?B?PGh0dHBzOi8vOWZhbnMudG9waWNib3guY29tL2dyb3Vwcy85?= =?UTF-8?B?ZmFucy9UZjZlMGIxYjNmODBkZjgyMS1NYWFjYjRjYzBhOGI1NjYzNzBjOTNi?= =?UTF-8?B?YTMxPg==?= List-Help: List-Id: "9fans" <9fans.9fans.net> List-Post: List-Software: Topicbox v0 List-Subscribe: Precedence: list Reply-To: 9fans <9fans@9fans.net> Content-Transfer-Encoding: 7bit List-Unsubscribe: , Topicbox-Delivery-ID: 2:9fans:437d30aa-c441-11e9-8a57-d036212d11b0:522be890-2105-11eb-b15e-8d699134e1fa:Maacb4cc0a8b566370c93ba31:1:9dJFdQ_cEBEhevUwgx2wifo08fytbABK7TLcTxwo9TE --000000000000cea23a0647cf3371 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable you can't avoid M mode on riscv, ever. There are several trap cases that will drop you in to M mode. And M mode does not have paging, so it will always be using what x86 would call real memory addresses. Given that, the more I look at this, the more I want Plan 9 KVA do be 0->1<<60 or so, and UVA to be above that. I have not yet seen a reason this won't work. It's just not like an x86 :-) thanks Ron P.S. Richard, this is all your fault, your comment a few days ago got me to thinking. Always a bad idea :-) On Wed, Jan 7, 2026 at 5:46=E2=80=AFAM Richard Miller <9fans@hamnavoe.com> = wrote: > : > > M mode, for > > example, has no virtual addressing, and it would be useful (to say the > > least) to have kernel and M mode have a common set of addresses. >=20 > Basic question: when would you use M mode? Doesn't the kernel normally > run entirely in Supervisor mode? Will the firmware on your platform even > allow Plan 9 to get into M mode? >=20 ------------------------------------------ 9fans: 9fans Permalink: https://9fans.topicbox.com/groups/9fans/Tf6e0b1b3f80df821-Maacb4= cc0a8b566370c93ba31 Delivery options: https://9fans.topicbox.com/groups/9fans/subscription --000000000000cea23a0647cf3371 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
you can't avoid M mode on riscv, ever. The= re are several trap cases that will drop you in to M mode.

=
And M mode does not have paging, so it will always be using what x86 w= ould call real memory addresses. 

Give= n that, the more I look at this, the more I want Plan 9 KVA do be 0->1&l= t;<60 or so, and UVA to be above that. 

= I have not yet seen a reason this won't work. It's just not like an= x86 :-)

thanks
Ron

P.S. Richard, this is all your fault, your comment a few days ago = got me to thinking. Always a bad idea :-)

On W= ed, Jan 7, 2026 at 5:46 AM Richard Miller <9fans@hamnavoe.com> wrote:
<rminnich@gma= il.com>:
> M mode, for
> example, has no virtual addressing, and it would be useful (to say the=
> least) to have kernel and M mode have a common set of addresses.
=
Basic question: when would you use M mode? Doesn't the kernel normally<= br /> run entirely in Supervisor mode? Will the firmware on your platform even allow Plan 9 to get into M mode?


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