From mboxrd@z Thu Jan 1 00:00:00 1970 To: 9fans@cse.psu.edu Subject: Re: [9fans] any vga driver gurus about? Date: Mon, 25 Sep 2000 22:05:12 +0100 From: nigel@9fs.org MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="upas-tyhcjyyzxkcymlmkbcxyjyufph" Message-Id: Topicbox-Message-UUID: 0dcf1b68-eac9-11e9-9e20-41e7f4b1d025 This is a multi-part message in MIME format. --upas-tyhcjyyzxkcymlmkbcxyjyufph Content-Disposition: inline Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit The in memory version is maintained as 16 bits to allow some overflow in calculations, such as horizontal counts. The original 6845 core was extended in the design of the vga to allow the generation of wider displays. The original width register was too small, so bits in other registers were borrowed to extend the basic register. By using a 16 bit in-memory register, the standard calculation could be done, and then the overflow bits copied to the right place. This explains what you are seeing. If you have not done this before, I strongly recommend getting a working system you can play with. This is not known as vga Hell for nothing. You should also read a good book on the history of the vga to understand the full horror. Which chip is it that is not supported? I would have thought all the Cirrus CL-GD chips were supported. --upas-tyhcjyyzxkcymlmkbcxyjyufph Content-Type: message/rfc822 Content-Disposition: inline Received: from finch-punt-12.mail.demon.net ([194.217.242.36]) by cpu; Mon Sep 25 21:51:25 BST 2000 Received: from punt-1.mail.demon.net by mailstore for ngr@cotswold.demon.co.uk id 969914838:10:25570:3; Mon, 25 Sep 2000 20:47:18 GMT Received: from hearno.cyberware.co.uk ([194.74.221.2]) by punt-1.mail.demon.net id aa1120396; 25 Sep 2000 20:47 GMT Received: from mail (postfix@psuvax1.cse.psu.edu [130.203.4.6]) by hearno.cyberware.co.uk (8.9.1b+Sun/8.7.2) with ESMTP id VAA18390 for ; Mon, 25 Sep 2000 21:46:21 +0100 (BST) Received: from psuvax1.cse.psu.edu (unknown [130.203.20.6]) by mail (CSE Mail Server) with ESMTP id 64A2A199D1; Mon, 25 Sep 2000 16:47:07 -0400 (EDT) Received: from mta06-svc.ntlworld.com (mta06-svc.ntlworld.com [62.253.162.46]) by mail (CSE Mail Server) with ESMTP id 02078199CC for <9fans@cse.psu.edu>; Mon, 25 Sep 2000 16:45:57 -0400 (EDT) Received: from freeze ([62.254.2.198]) by mta06-svc.ntlworld.com (InterMail vM.4.01.02.27 201-229-119-110) with SMTP id <20000925204541.QDLF19246.mta06-svc.ntlworld.com@freeze> for <9fans@cse.psu.edu>; Mon, 25 Sep 2000 21:45:41 +0100 Message-ID: <003b01c02731$8823c420$0301a8c0@freeze> From: "Matt" To: "9fans" <9fans@cse.psu.edu> Date: Mon, 25 Sep 2000 21:45:18 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 Subject: [9fans] any vga driver gurus about? Sender: 9fans-admin@cse.psu.edu Errors-To: 9fans-admin@cse.psu.edu X-BeenThere: 9fans@cse.psu.edu X-Mailman-Version: 2.0beta4 Precedence: bulk Reply-To: 9fans@cse.psu.edu List-Id: Fans of the O/S Plan 9 from Bell Labs <9fans.cse.psu.edu> Hi, Okay I've ended up having to try and write a vga driver for my laptop a challenge to which I have never risen before It's partiularly intriguing as I've not even got a running plan9 to compile it with I'm reading through stuff and I've come across something I don't understand in http://offworld.fac.cs.cmu.edu/plan9/source/src/cmd/aux/vga/vga.h the crt registers are defined as ushorts 125 typedef struct Vga { 129 ushort crt[256]; in my cl-gd52x manual the CRT registers are 8 bits in http://offworld.fac.cs.cmu.edu/plan9/source/src/cmd/aux/vga/clgd542x.c which is the driver file I'm studying there is some stuff like this : 248 if(vga->crt[0x16] & 0x100) 249 vga->crt[0x1A] |= 0x40; 250 if(vga->crt[0x16] & 0x200) 251 vga->crt[0x1A] |= 0x80; these set the vertical blank end overflows (whatever they are :) 253 if(vga->crt[0x13] & 0x100) 254 vga->crt[0x1B] |= 0x10; this sets the blanking control to 1 which enables the blanking set in CR1A so what use is & ing an 8bit value with a 16bit value? Matt --upas-tyhcjyyzxkcymlmkbcxyjyufph--