Re: [9fans] dumb kw question

[Charles Forsyth <forsyth@terzarima.net>]

>ether1116.c:573: 		cachedwbse(&r->cs, BY2SE);

led me to read:

		/* set up receive descriptor */
		r = &ctlr->rx[ctlr->rxtail];
		assert(((uintptr)r & (Descralign - 1)) == 0);
		r->countsize = Bufsize(Rxblklen);
		r->buf = PADDR(b->rp);
		cachedwbse(r, sizeof *r);
		l2cacheuwbse(r, sizeof *r);

		/* and fire */
		r->cs = RCSdmaown | RCSenableintr;
		cachedwbse(&r->cs, BY2SE);
		l2cacheuwbse(&r->cs, BY2SE);

if Descralign is 16, and sizeof(Rx) is 16, but the cache line size is 32,
i'm surprised it works. there are two descriptors per cache line,
and two processors, but only one sees both caches. the other processor -
the ethernet controller - depending how it's wired up,
sees at best L2 but more usually uncached RAM. i don't see how this cache
flushing (and invalidation elsewhere) can give a coherent view of both descriptors.

i'd expect to see peculiar errors, such as non-trivial levels of retransmission
(both sides) causing poor performance.