Re: [9fans] sparc compiler bug

[Charles Forsyth <forsyth@terzarima.net>]

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only the linker knows the details, so any change would be made to kl.
it's using the same approach for inherently 2-address FP instructions as
it does for 3 address FP/INT instructions where only two operands are specified
(set the third register to one of the others).

i know the change needed but i'm curious whether they've added a trap
check to the hardware that wasn't there before, or whether it's just
something else complaining (but the hardware still doesn't).

when i say i know the change needed, i'm assuming i'm `supposed'
to set the field to 0 (even though that's also a valid register number).
i can't find my sparc handbook today.

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From: Tim Newsham <newsham@lava.net>
To: 9fans@cse.psu.edu
Subject: [9fans] sparc compiler bug
Date: Sun, 9 Jan 2005 12:52:49 -1000 (HST)
Message-ID: <Pine.BSI.4.58.0501091248230.10670@malasada.lava.net>

When generating conversion like "FsTOd" the compiler
is generating invalid opcodes.  The format for this
and related instructions has an rs2 and an rd field but
designates the rs1 field as reserved.  The compiler/assembler/linker
is generating:

    opcode=FsToD, rd=6, rs1=6, rs2=10

for the opcode "FSTOD F10, F6."  This is an illegal use of a
reserved field.  I've tried to track this down
but I'm still unfamiliar with the compiler suite.

Tim N.