From mboxrd@z Thu Jan 1 00:00:00 1970 From: erik quanstrom Date: Fri, 19 Oct 2012 11:46:39 -0400 To: 9fans@hamnavoe.com, 9fans@9fans.net Message-ID: In-Reply-To: <1860770efaae1076bc9ee9fbcf68fdd2@hamnavoe.com> References: <1860770efaae1076bc9ee9fbcf68fdd2@hamnavoe.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [9fans] sheevaplug SD card driver Topicbox-Message-UUID: c0ffdc96-ead7-11e9-9d60-3106f5b1d025 On Fri Oct 19 11:40:41 EDT 2012, 9fans@hamnavoe.com wrote: > > easiest to just > > cacheline-align everything in malloc >=20 > Might be a good idea for ARM. Until someone produces a > chip with gigantic cache lines? >=20 > Another alternative might be to have a separate pool of > uncached memory. i'm certainly not claiming this is a general solution for all possible arms, but for kw-style caches (16-byte lines) and kw-style hardware (very little cache-coherency), i think the idea has a lot of merit. especially with quickfit with external (that is cache-coherent) tracking. i really do like your cc malloc, though. very clean. though i had to look twice to verify i understood the pointer orthodontics. =E2=98=BA. - erik