From: Richard Miller <9fans@hamnavoe.com>
To: 9fans@9fans.net
Subject: Re: [9fans] risc-v memory layout
Date: Wed, 7 Jan 2026 19:42:21 +0000 [thread overview]
Message-ID: <ea359f4c9da90ed3a9a0d90e19442ab2@hamnavoe.com> (raw)
In-Reply-To: <CAP6exYKF_GEJpdEOPidscc_J7ezkUCU4DAsFVu4cGzahJBPJkQ@mail.gmail.com>
rminnich@gmail.com:
> you can't avoid M mode on riscv, ever. There are several trap cases that
> will drop you in to M mode.
I thought avoiding M mode was forced on you by the SBI implementation
(firmware), which intercepts M mode traps and delegates them to S mode
(if it feels like it). That's my recollection from working with the
Polarfire Icicle, but it's a few years back. Or are you designing for
a bare metal platform with no SBI?
Are there any riscv implementations on the market which allow kernel
and user mode to run with different XLEN, and thus enable a 64-bit
kernel to host 32-bit processes? If so, I think that implies that
you would want user address space to start at (or near) zero.
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next prev parent reply other threads:[~2026-01-07 20:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-06 23:13 [9fans] risc-v memory layout ron minnich
2026-01-07 9:44 ` Richard Miller
2026-01-07 16:58 ` ron minnich
2026-01-07 19:42 ` Richard Miller [this message]
2026-01-07 21:01 ` Fwd: " ron minnich
2026-01-07 17:54 ` tlaronde
2026-01-07 19:28 ` ron minnich
2026-01-08 2:50 ` Dan Cross
2026-01-08 8:08 ` tlaronde
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