From mboxrd@z Thu Jan 1 00:00:00 1970 MIME-Version: 1.0 Message-ID: From: "kernel panic" To: "Fans of the OS Plan 9 from Bell Labs" <9fans@9fans.net> Content-Type: text/plain; charset=UTF-8 Date: Tue, 30 Apr 2013 12:15:41 +0200 In-Reply-To: <3c4b2633fc424165a74427a393f539ec@hamnavoe.com> References: <3c4b2633fc424165a74427a393f539ec@hamnavoe.com> Subject: Re: [9fans] 5l bug Topicbox-Message-UUID: 4c5098b2-ead8-11e9-9d60-3106f5b1d025 > Gesendet: Montag, 29. April 2013 um 21:34 Uhr > Von: "Richard Miller" <9fans@hamnavoe.com> > An: 9fans@9fans.net > Betreff: Re: [9fans] 5l bug > > > following up, theres my naive fix for this. instead of > > emiting conditional division instruction by 5c... dont and > > keep the branch. does this make any sense? > > I think it should be corrected in 5l. Some ARM versions do > have a hardware divide instruction, which could one day be > supported by 5l, so 5c should be kept more generic. The compiler already assumes things that would be not true for native divide instructions. For example, we assume that divide modifies the condition flags, which would not be the case for native SDIV/UDIV, but is the case for the emulated ones because its implemented as a subroutine: (from /sys/src/cmd/5c/peep.c) /* * Depends on an analysis of the encodings performed by 5l. * These seem to be all of the opcodes that lead to the "S" bit * being set in the instruction encodings. * * C_SBIT may also have been set explicitly in p->scond. */ int modifiescpsr(Prog *p) { return (p->scond&C_SBIT) || p->as == ATST || p->as == ATEQ || p->as == ACMN || p->as == ACMP || p->as == AMULU || p->as == ADIVU || p->as == AMUL || p->as == ADIV || p->as == AMOD || p->as == AMODU || p->as == ABL; } the change i made just avoids the branch optimization for these instructions not executing them conditionally. the whole idea of this pass is to avoid the branching arround *short* conditional code sequences (4 instructions at max). with the emulated instructions the _div call setup already takes more than 4 instructions and just reintroducing a branch in the linker counters what the optimization pass tried to archive in the first place. but maybe its not really worth thinking about because conditional divide seems quite rare (?) and emulated divide will be slow in any case (?) so it wont matter if we readd conditional branch in the linker? still, the dependency between 5l <-> 5c above remains... otherwise, one would need to write condition flag preserving version... for these instructions to make them behave exactly like the native instructions... perhaps emulate the instructions by traping in the kernel? seems even slower... how ignorant do we want 5c to be at what cost? -- cinap