From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=DATE_IN_PAST_12_24,DKIM_SIGNED, DKIM_VALID autolearn=no autolearn_force=no version=3.4.4 Received: (qmail 6358 invoked from network); 30 Jan 2021 19:05:04 -0000 Received: from 1ess.inri.net (216.126.196.35) by inbox.vuxu.org with ESMTPUTF8; 30 Jan 2021 19:05:04 -0000 Received: from a48-181.smtp-out.amazonses.com ([54.240.48.181]) by 1ess; Fri Jan 29 21:43:52 -0500 2021 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=224i4yxa5dv7c2xz3womw6peuasteono; d=amazonses.com; t=1611974623; h=From:Content-Type:Content-Transfer-Encoding:Mime-Version:Subject:Date:References:To:In-Reply-To:Message-Id:Feedback-ID; bh=OVbt2Uf9wwVL1KZLqv/1DF/SKFSZHzCRGCvZ8u9svbk=; b=fBgAeuZlcILwDHTy/I1HtVXSUfXEwRXM5e8chsJRpiKoaxqiE3sxwgjWr/QxzzYj R6FO/JewW/EaO7C338VTbwyy6MKbSvYqfXOaI9OPsHo6VlIef2uNg8k3Lx+zLRh7GKN ZMIDfEOXLbKvNtmfJnk4TU3sbRQ9YXMnQcE2c9hY= X-Default-Received-SPF: pass (skip=loggedin (res=PASS)) x-ip-name=50.202.122.66; envelope-from=; From: Mack Wallace Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.1\)) Date: Sat, 30 Jan 2021 02:43:43 +0000 References: To: 9front@9front.org In-Reply-To: Message-ID: <01000177512cbf36-f7a8198c-3461-4d02-b5b4-24dc0287284e-000000@email.amazonses.com> X-Mailer: Apple Mail (2.3608.120.23.2.1) X-Authenticated-User: mackbw@mapinternet.com X-SES-Outgoing: 2021.01.30-54.240.48.181 Feedback-ID: 1.us-east-1.X+xhoL9JiEQ8K0gzGjV36WZnSewOzOs8YCWuakKsLBY=:AmazonSES List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: module configuration interface-oriented high-performance locator Subject: Re: [9front] 9front on Raspberry Pi 400 Reply-To: 9front@9front.org Precedence: bulk Unfortunately, no luck on that=E2=80=A6 Output of the Pi 400 below. At least now I have the serial console, much easier to cut and paste - = although I shortened the repeated errors. Wondering if I should set up a cpu/auth - setup remote access, and let = you work that way - although the serial adapter I got to work is USB to = TTL serial. I couldn=E2=80=99t get my RS-232 to TTL adapter to work - I = presume that=E2=80=99s because the Pi doesn=E2=80=99t have enough = amperage to drive it / or the USB to serial I have doesn=E2=80=99t wont = supply enough current the other way. So I wonder whether the Adafruit = USB to TTL serial adapter can be seen by 9.=20 Mack 127 holes free 0x00500000 0x3e600000 1041235968 1041235968 bytes free Plan 9 intrsoff: GIC intids [0-31]: 01ff0000 are locked in disable state intrsoff: GIC intids [0-31]: 0000ffff are locked in enable state cpu0: 1800MHz ARM Cortex-A72 r0p3 4006M memory: 998M kernel data, 3008M user, 15011M swap *pciwin: 0x600000000 0x640000000 *pcidmawin: 0x0 0x100000000 pcienable PCI.0.0.0: pcr 0->7 pcienable PCI.1.0.0: pcr 0->2 bus dev type vid did intl memory 0 0/0 06 04 00 14e4 2711 0 ioa:00000000-00001000 4096 = mema:600000000-600100000 1048576 ->1 1 0/0 0c 03 30 1106 3483 0 0:600000004 4096 #l0: genet: 1000Mbps port 0xFFFFFFFFBD580000 irq 189 ea dca632e63357 usbxhci: cpu3: 1800MHz ARM Cortex-A72 r0p3 cpu1: 1800MHz ARM Cortex-A72 r0p3 cpu2: 1800MHz ARM Cortex-A72 r0p3 0x1106 0x3483: port 600000000 size 4096 irq 0 xhci 600000000: controller not ready before reset: 00000815 xhci 600000000: controller not halted after reset: 00000815 xhci 600000000: controller not ready after run: 0000080d #l0: phy1 id 600d84a2 oui 80361 xhci 600000000: controller not ready before reset: 0000080d sdhc: read error intr 2008002 stat 1fff0000 ... sdhc: read error intr 2008002 stat 1fff0000 /dev/sdM0: BCM SD Host Controller 02 Version 10 sdhc: read error intr 2008002 stat 1fff0000 ... sdhc: read error intr 2008002 stat 1fff0000 /dev/sdM0/data bootargs is (tcp, tls, il, local!device)[] xhci 600000000: controller = not halted after reset: 00000811 xhci 600000000: controller not ready after run: 0000080d xhci 600000000: controller not ready before reset: 0000080d xhci 600000000: controller not halted after reset: 00000811 xhci 600000000: controller not ready after run: 0000080d ... xhci 600000000: controller not halted after reset: 00000811 xhci 600000000: controller not ready after run: 0000080d xhci 600000000: controller not ready before reset: 0000080d ... [SERIAL/DIRECT] DISCONNECT > On Jan 29, 2021, at 9:58 AM, cinap_lenrek@felloff.net wrote: >=20 > ok, here we go. >=20 > i wrote some code to extract the dma-rangles property from > the device tree and apply it to the pci express code. >=20 > this adds new kernel variables *pciwin and *pcidmawin, > that reflect the setting. they get filled in by the > device tree setting when booted from firmware, > but can be overridden in cmdline.txt or when we /dev/reboot. >=20 > new kernel images to try: >=20 > http://felloff.net/usr/cinap_lenrek/9pi4-pciwin (image = for sdcard) > http://felloff.net/usr/cinap_lenrek/s9pi4-pciwin (kernel with = debug symbols) >=20 > sha1sums: >=20 > 9b8775e9b9b9daebbd72cde308c2b7117d2d065b 9pi4 > 0a01ed1555e99f847ba9eab8e8693364d4839f2c s9pi4 >=20 > what follows is a example bootmessage from my pi4 8GB. > note that in your case, the *pcidmawin print below should be = different. > please report back what you get as output there. >=20 > Plan 9 > intrsoff: GIC intids [0-31]: 01ff0000 are locked in disable state > intrsoff: GIC intids [0-31]: 0000ffff are locked in enable state > cpu0: 1500MHz ARM Cortex-A72 r0p3 > 8102M memory: 998M kernel data, 7104M user, 31395M swap > *pciwin: 0x600000000 0x604000000 > *pcidmawin: 0x0 0xc0000000 > pcienable PCI.0.0.0: pcr 0->7 > pcienable PCI.1.0.0: pcr 0->2 > bus dev type vid did intl memory > 0 0/0 06 04 00 14e4 2711 0 ioa:00000000-00001000 4096 = mema:600000000-600100000 1048576 ->1 > 1 0/0 0c 03 30 1106 3483 0 0:600000004 4096=20 > #l0: genet: 1000Mbps port 0xFFFFFFFFBD580000 irq 189 ea dca632b1adfe > usbxhci: cpu2: 1500MHz ARM Cortex-A72 r0p3 > cpu3: 1500MHz ARM Cortex-A72 r0p3 > cpu1: 1500MHz ARM Cortex-A72 r0p3 > 0x1106 0x3483: port 600000000 size 4096 irq 0 > #l0: phy1 id 600d84a2 oui 80361 >=20 > patch: >=20 > diff -r 5c327eddc496 sys/src/9/bcm/bootargs.c > --- a/sys/src/9/bcm/bootargs.c Sat Jan 23 20:36:09 2021 -0800 > +++ b/sys/src/9/bcm/bootargs.c Fri Jan 29 15:45:16 2021 +0100 > @@ -12,6 +12,7 @@ > static char *confval[MAXCONF]; > static int nconf; > static char maxmem[256]; > +static char pciwin[38], pcidmawin[38]; >=20 > static int > findconf(char *k) > @@ -89,23 +90,23 @@ > static void > devtreeprop(char *path, char *key, void *val, int len) > { > + uvlong addr, size; > + uchar *p =3D val; > + char *s; > + > if((strcmp(path, "/memory") =3D=3D 0 || strcmp(path, = "/memory@0") =3D=3D 0) > && strcmp(key, "reg") =3D=3D 0){ > if(findconf("*maxmem") < 0 && len > 0 && (len % (3*4)) = =3D=3D 0){ > - uvlong top; > - uchar *p =3D val; > - char *s; > - > - top =3D (uvlong)beget4(p)<<32 | beget4(p+4); > - top +=3D beget4(p+8); > - s =3D seprint(maxmem, &maxmem[sizeof(maxmem)], = "%#llux", top); > + addr =3D (uvlong)beget4(p)<<32 | beget4(p+4); > + addr +=3D beget4(p+8); > + s =3D seprint(maxmem, &maxmem[sizeof(maxmem)], = "%#llux", addr); > p +=3D 3*4; > len -=3D 3*4; > while(len > 0){ > - top =3D (uvlong)beget4(p)<<32 | = beget4(p+4); > - s =3D seprint(s, = &maxmem[sizeof(maxmem)], " %#llux", top); > - top +=3D beget4(p+8); > - s =3D seprint(s, = &maxmem[sizeof(maxmem)], " %#llux", top); > + addr =3D (uvlong)beget4(p)<<32 | = beget4(p+4); > + s =3D seprint(s, = &maxmem[sizeof(maxmem)], " %#llux", addr); > + addr +=3D beget4(p+8); > + s =3D seprint(s, = &maxmem[sizeof(maxmem)], " %#llux", addr); > p +=3D 3*4; > len -=3D 3*4; > } > @@ -113,6 +114,20 @@ > } > return; > } > + if(strncmp(path, "/scb/pcie@", 10) =3D=3D 0 && len =3D=3D (3*4 + = 4*4)){ > + p +=3D 3*4; > + addr =3D (uvlong)beget4(p)<<32 | beget4(p+4); > + p +=3D 2*4; > + size =3D (uvlong)beget4(p)<<32 | beget4(p+4); > + if(strcmp(key, "ranges") =3D=3D 0 && findconf("*pciwin") = < 0){ > + snprint(pciwin, sizeof(pciwin), "%#llux %#llux", = addr, addr+size); > + addconf("*pciwin", pciwin); > + } else if(strcmp(key, "dma-ranges") =3D=3D 0 && = findconf("*pcidmawin") < 0){ > + snprint(pcidmawin, sizeof(pcidmawin), "%#llux = %#llux", addr, addr+size); > + addconf("*pcidmawin", pcidmawin); > + } > + return; > + } > if(strcmp(path, "/chosen") =3D=3D 0 && strcmp(key, "bootargs") = =3D=3D 0){ > if(len > BOOTARGSLEN) > len =3D BOOTARGSLEN; > diff -r 5c327eddc496 sys/src/9/bcm64/dat.h > --- a/sys/src/9/bcm64/dat.h Sat Jan 23 20:36:09 2021 -0800 > +++ b/sys/src/9/bcm64/dat.h Fri Jan 29 15:44:26 2021 +0100 > @@ -249,7 +249,8 @@ > uintptr physio; > uintptr virtio; > uintptr armlocal; > - uintptr pciwin; > + uintptr pciwin; /* PCI outbound window CPU->PCI */ > + uintptr pcidmawin; /* PCI inbound window PCI->DRAM */ > int oscfreq; > }; > extern Soc soc; > diff -r 5c327eddc496 sys/src/9/bcm64/io.h > --- a/sys/src/9/bcm64/io.h Sat Jan 23 20:36:09 2021 -0800 > +++ b/sys/src/9/bcm64/io.h Fri Jan 29 15:43:55 2021 +0100 > @@ -6,5 +6,5 @@ > IRQether =3D IRQgic + 29, > }; >=20 > -#define PCIWINDOW 0 > +#define PCIWINDOW soc.pcidmawin > #define PCIWADDR(va) (PADDR(va)+PCIWINDOW) > diff -r 5c327eddc496 sys/src/9/bcm64/pcibcm.c > --- a/sys/src/9/bcm64/pcibcm.c Sat Jan 23 20:36:09 2021 -0800 > +++ b/sys/src/9/bcm64/pcibcm.c Fri Jan 29 15:43:55 2021 +0100 > @@ -244,6 +244,16 @@ > pcibcmlink(void) > { > int log2dmasize =3D 30; // 1GB > + char *s; > + > + if((s =3D getconf("*pciwin")) !=3D nil){ > + print("*pciwin: %s\n", s); > + soc.pciwin =3D (uintptr)strtoll(s, nil, 16); > + } > + if((s =3D getconf("*pcidmawin")) !=3D nil){ > + print("*pcidmawin: %s\n", s); > + soc.pcidmawin =3D (uintptr)strtoll(s, nil, 16); > + } >=20 > regs[RGR1_SW_INIT_1] |=3D 3; > delay(200); > @@ -266,8 +276,8 @@ > // SCB_ACCESS_EN, CFG_READ_UR_MODE, MAX_BURST_SIZE_128, SCB0SIZE > regs[MISC_MISC_CTRL] =3D 1<<12 | 1<<13 | 0<<20 | = (log2dmasize-15)<<27; >=20 > - regs[MISC_RC_BAR2_CONFIG_LO] =3D (log2dmasize-15); > - regs[MISC_RC_BAR2_CONFIG_HI] =3D 0; > + regs[MISC_RC_BAR2_CONFIG_LO] =3D ((u32int)soc.pcidmawin & ~0x1F) = | (log2dmasize-15); > + regs[MISC_RC_BAR2_CONFIG_HI] =3D soc.pcidmawin >> 32; >=20 > regs[MISC_RC_BAR1_CONFIG_LO] =3D 0; > regs[MISC_RC_BAR3_CONFIG_LO] =3D 0; >=20 > -- > cinap >=20