From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mta01.eonet.ne.jp ([203.140.81.47]) by ur; Fri Aug 19 19:01:50 EDT 2016 Received: from ci5dell.jitaku.localdomain (182-164-123-249f1.osk3.eonet.ne.jp [182.164.123.249]) by mailmsa12.mozu.eo.k-opti.ad.jp with ESMTP id u7JN1hkY022405 for <9front@9front.org>; Sat, 20 Aug 2016 08:01:43 +0900 To: 9front@9front.org Subject: Re: [9front] core-i5(TypeSNB) and vesa mode Date: Sat, 20 Aug 2016 08:01:43 +0900 From: kokamoto@hera.eonet.ne.jp Message-ID: <01d4f478ff2772119d71f878f3083f93@ci5dell.jitaku.localdomain> In-Reply-To: <70a744b447e8e4bef5ebb8764917da47@ci5dell.jitaku.localdomain> References: <02306a9665f1c5940399bdfce56925c3@felloff.net> <3ae4e44eae5fb0aa1f6fc92a40132703@ci5dell.jitaku.localdomain> <70a744b447e8e4bef5ebb8764917da47@ci5dell.jitaku.localdomain> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="upas-fdhzpaqcwexozjxxnuawacstnw" List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: reduce/map element controller This is a multi-part message in MIME format. --upas-fdhzpaqcwexozjxxnuawacstnw Content-Disposition: inline Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit After I posted the sysinfo of Dell-790 machine, I intended to make another 0x29a2 did old machine work, and then post the results. However, I got much tired, and can't do anything now. It may continue one month or so. Therefore, I'll post the diff to the last cdrom for Dell790 sandy-bridge machine to work up to 1680x1050x32 resolution, not work for DP/HDMI, though. This patch includes the one posted by cinap before. It was made by the command: diff -n /sys/src/cmd/aux/vga/igfx.c /n/cdrom/sys/src/cmd/aux/vga/igfx.c. Kenji --upas-fdhzpaqcwexozjxxnuawacstnw Content-Disposition: inline Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit /sys/src/cmd/aux/vga/igfx.c:92,93 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:91 < Reg rxiir; /* FDI_RX_IIR */ < Reg rximr; /* FDI_RX_IMR */ /sys/src/cmd/aux/vga/igfx.c:221,222 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:218 < < /* South Display Engine */ /sys/src/cmd/aux/vga/igfx.c:227,233 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:223,229 < t->ht = snarfreg(igfx, o + 0x00000); /* HTOTAL */ < t->hb = snarfreg(igfx, o + 0x00004); /* HBLANK */ < t->hs = snarfreg(igfx, o + 0x00008); /* HSYNC */ < t->vt = snarfreg(igfx, o + 0x0000C); /* VTOTAL */ < t->vb = snarfreg(igfx, o + 0x00010); /* VBLANK */ < t->vs = snarfreg(igfx, o + 0x00014); /* VSYNC */ < t->vss = snarfreg(igfx, o + 0x00028); /* VSYNCSHIFT for interlaced */ --- > t->ht = snarfreg(igfx, o + 0x00000); > t->hb = snarfreg(igfx, o + 0x00004); > t->hs = snarfreg(igfx, o + 0x00008); > t->vt = snarfreg(igfx, o + 0x0000C); > t->vb = snarfreg(igfx, o + 0x00010); > t->vs = snarfreg(igfx, o + 0x00014); > t->vss = snarfreg(igfx, o + 0x00028); /sys/src/cmd/aux/vga/igfx.c:248,255 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:244,251 < t->dm[0] = snarfreg(igfx, o + 0x30); /* Data M1 value (transcoder A) */ < t->dn[0] = snarfreg(igfx, o + 0x34); /* Data N value (transcoder A) */ < t->dm[1] = snarfreg(igfx, o + 0x38); /* Data M2 value (transcoder A) */ < t->dn[1] = snarfreg(igfx, o + 0x3c); /* Data N2 value (transcoder A */ < t->lm[0] = snarfreg(igfx, o + 0x40); /* Data Link M1 value (transcoder A) */ < t->ln[0] = snarfreg(igfx, o + 0x44); /* Data Link N1 value (transcoder A) */ < t->lm[1] = snarfreg(igfx, o + 0x48); /* Data Link M2 value (transcoder A) */ < t->ln[1] = snarfreg(igfx, o + 0x4c); /* Data Link N2 value (transcoder A) */ --- > t->dm[0] = snarfreg(igfx, o + 0x30); > t->dn[0] = snarfreg(igfx, o + 0x34); > t->dm[1] = snarfreg(igfx, o + 0x38); > t->dn[1] = snarfreg(igfx, o + 0x3c); > t->lm[0] = snarfreg(igfx, o + 0x40); > t->ln[0] = snarfreg(igfx, o + 0x44); > t->lm[1] = snarfreg(igfx, o + 0x48); > t->ln[1] = snarfreg(igfx, o + 0x4c); /sys/src/cmd/aux/vga/igfx.c:269 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:265 < snarftrans(igfx, p, o); /* HTOTAL Horizontal Total */ --- > snarftrans(igfx, p, o); /sys/src/cmd/aux/vga/igfx.c:271 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:267 < p->src = snarfreg(igfx, o + 0x0001C); /* SRCSZ source image size */ --- > p->src = snarfreg(igfx, o + 0x0001C); /sys/src/cmd/aux/vga/igfx.c:279 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:274 < /* display port control */ /sys/src/cmd/aux/vga/igfx.c:298,299 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:293,294 < p->dsp->stride = snarfreg(igfx, 0x70188 + x*0x1000); < p->dsp->tileoff = snarfreg(igfx, 0x701A4 + x*0x1000); --- > p->dsp->stride = snarfreg(igfx, 0x70188 + x*0x1000); > p->dsp->tileoff = snarfreg(igfx, 0x701A4 + x*0x1000); /sys/src/cmd/aux/vga/igfx.c:304 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:300 > case TypeSNB: /sys/src/cmd/aux/vga/igfx.c:312,313 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:308 < /* wet floor */ < case TypeSNB: --- > /sys/src/cmd/aux/vga/igfx.c:329 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:323 < case 0x0102: /* Dell Optiplex 790 */ /sys/src/cmd/aux/vga/igfx.c:333 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:326 < case 0x29a2: /* 82P965/G965 HECI desktop */ /sys/src/cmd/aux/vga/igfx.c:407 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:400 < igfx->ppcontrol = snarfreg(igfx, 0x61204); --- > igfx->ppcontrol = snarfreg(igfx, 0x61204); /sys/src/cmd/aux/vga/igfx.c:414 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:407 < igfx->cdclk = 300; /* Core Display Clock MHz */ --- > igfx->cdclk = 300; /* MHz */ /sys/src/cmd/aux/vga/igfx.c:495 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:489 > /sys/src/cmd/aux/vga/igfx.c:576,579 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:569 < < print("freq=%lld, cref=%d, m1=%ud, m2=%ud, n=%ud,p1=%ud,p2=%ud\n", a, cref, *m1,*m2,*n,*p1,P2); /* K.Okamoto */ < print("fitted frequency = %ulld\n", (uvlong)cref*(5*(*m1+2)+(*m2+2))/(*n+2)/(*p1*P2)); < /sys/src/cmd/aux/vga/igfx.c:611,623 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:600 < /* transcoder dpll enable */ < igfx->dpllsel.v |= 8<<(x*4); < /* program rawclock to 125MHz */ < igfx->rawclkfreq.v = 125; < if(port == PortLCD){ < igfx->drefctl.v |= 2<<11; < igfx->drefctl.v |= 1; < } else{ < igfx->drefctl.v |= 2<<9; < // igfx->drefctl.v |= 2<<11; < // igfx->drefctl.v |= 1; < } < goto PCHcommon1; /sys/src/cmd/aux/vga/igfx.c:628,629 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:605 < // igfx->rawclkfreq.v = 125; < igfx->rawclkfreq.v = rr(igfx, 0xC6204); /* K.Okamoto */ --- > igfx->rawclkfreq.v = 125; /sys/src/cmd/aux/vga/igfx.c:644 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:619 < PCHcommon1: /sys/src/cmd/aux/vga/igfx.c:658 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:633 < cref = getcref(igfx, x); /* cref=120MHz for TypeSNB, 96MHz for TypeG45 */ --- > cref = getcref(igfx, x); /sys/src/cmd/aux/vga/igfx.c:665 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:640 < dpll->ctrl.v &= ~(3<<24); /* reset FP1 P2 divide */ --- > dpll->ctrl.v &= ~(3<<24); /sys/src/cmd/aux/vga/igfx.c:677,678 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:652 < // if(freq > 225*MHz){ /* K.Okamoto */ < p2 >>= 1; /* p2 = 5 */ --- > p2 >>= 1; /sys/src/cmd/aux/vga/igfx.c:697,699 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:670 < //m1=14, m2=8, n=3, p1=2 K.Okamoto < // ctrl.a=c6014, dpll->fp0.a=c6048 K.Okamoto < //print("m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n", m1, m2, n, p1, p2); /sys/src/cmd/aux/vga/igfx.c:724 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:695 < u32int m, n; --- > uvlong m, n; /sys/src/cmd/aux/vga/igfx.c:727 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:698 < m = (n * (((uvlong)freq * bpp)/8)) / ((uvlong)lsclk * lanes); --- > m = (n * ((freq * bpp)/8)) / (lsclk * lanes); /sys/src/cmd/aux/vga/igfx.c:733 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:704 < m = ((uvlong)n * freq) / lsclk; --- > m = (n * freq) / lsclk; /sys/src/cmd/aux/vga/igfx.c:750 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:721 < /* trans/pipe enable */ --- > /* tans/pipe enable */ /sys/src/cmd/aux/vga/igfx.c:760 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:732 > /sys/src/cmd/aux/vga/igfx.c:786 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:759 > lanes = 1; /sys/src/cmd/aux/vga/igfx.c:788,792 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:760 < if((m->x * m->y) < 1680*1050) /* quick & dirty hack */ < lanes = 1; < else < lanes = 2; /* for 1680x1050x32 */ < /sys/src/cmd/aux/vga/igfx.c:794 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:762 < if(fdi->rxctl.a != 0){ /* TypeSNB or TypeIVB */ --- > if(fdi->rxctl.a != 0){ /sys/src/cmd/aux/vga/igfx.c:821 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:789 < fdi->rxtu[0].v = (tu-1)<<25; /* set tusize=tu-1 */ --- > fdi->rxtu[0].v = (tu-1)<<25; /sys/src/cmd/aux/vga/igfx.c:853 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:821 < /* disable vga compatibility */ --- > /* disable vga */ /sys/src/cmd/aux/vga/igfx.c:860 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:828,830 < igfx->adpa.v &= ~(1<<31); /* disable ADPA */ --- > igfx->adpa.v &= ~(1<<31); > if(igfx->type == TypeG45) > igfx->adpa.v |= (3<<10); /* Monitor DPMS: off */ /sys/src/cmd/aux/vga/igfx.c:891,893 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:861 < if(igfx->type == TypeG45) < x = (igfx->adpa.v >> 30) & 1; < if(igfx->type == TypeSNB || igfx->type == TypeIVB) --- > if(igfx->npipe > 2) /sys/src/cmd/aux/vga/igfx.c:894 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:863,864 > else > x = (igfx->adpa.v >> 30) & 1; /sys/src/cmd/aux/vga/igfx.c:897 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:867 < igfx->adpa.v &= ~(3<<10); /* Monitor DPMS: on */ --- > igfx->adpa.v &= ~(3<<10); /* Monitor DPMS: on */ /sys/src/cmd/aux/vga/igfx.c:906,913 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:875 < if(igfx->type == TypeSNB){ /* set DPMS VSYNC, HSYNC added K.Okamoto */ < igfx->adpa.v |= 3<<3; < if(m->hsync == '-') < igfx->adpa.v ^= 1<<3; < if(m->vsync == '-') < igfx->adpa.v ^= 1<<4; < igfx->pipe[x].fdi->dpctl.v ^= 1<<4; < } /sys/src/cmd/aux/vga/igfx.c:917,920 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:879,882 < if(igfx->type == TypeG45) < x = (igfx->lvds.v >> 30) & 1; /* pipe select 0/1 */ < if(igfx->type == TypeSNB || igfx->type == TypeIVB) < x = (igfx->lvds.v >> 29) & 3; /* transcoder A or B or C */ --- > if(igfx->npipe > 2) > x = (igfx->lvds.v >> 29) & 3; > else > x = (igfx->lvds.v >> 30) & 1; /sys/src/cmd/aux/vga/igfx.c:1084,1092 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1046,1048 < if(p->fdi->rxctl.a != 0){ /* TypeSNB or TypeIVB */ < if(igfx->type == TypeSNB){ < csr(igfx, 0xC6200, 1<<11, 2); /* pch ref souce & ssc enable */ < sleep(5); < csr(igfx, 0xC6200, 1<<0, 1); /* ssc1 enable */ < sleep(5); < } < p->fdi->rxctl.v &= ~(1<<31); /* disable */ < p->fdi->rxctl.v &= ~(1<<4); /* rawclk(not pcdclk) */ --- > if(p->fdi->rxctl.a != 0){ > p->fdi->rxctl.v &= ~(1<<31); > p->fdi->rxctl.v &= ~(1<<4); /* rawclk */ /sys/src/cmd/aux/vga/igfx.c:1100,1102 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1056,1057 < if(igfx->type != TypeSNB) < p->fdi->txctl.v &= ~(1<<31); /* disable */ < p->fdi->txctl.v |= (1<<14); /* enable FDI pll */ --- > p->fdi->txctl.v &= ~(1<<31); > p->fdi->rxctl.v |= (1<<14); /* enable pll */ /sys/src/cmd/aux/vga/igfx.c:1149,1151 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1103 < if (igfx->type == TypeSNB){ < /* unmask bit lock and symbol lock bits */ < csr(igfx, p->fdi->rximr.a, 3<<8, 0); /sys/src/cmd/aux/vga/igfx.c:1153,1156 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1105,1108 < p->fdi->rxctl.v &= ~(3<<8); /* link train pattern1 */ < p->fdi->rxctl.v |= 1<<31; /* enable */ < loadreg(igfx, p->fdi->rxctl); < --- > p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 00 */ > p->fdi->rxctl.v |= 1<<10; /* auto train enable */ > p->fdi->rxctl.v |= 1<<31; /* enable */ > loadreg(igfx, p->fdi->rxctl); /sys/src/cmd/aux/vga/igfx.c:1158,1160 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1110,1113 < p->fdi->txctl.v &= ~(3<<8); /* link train pattern1 */ < p->fdi->txctl.v |= 1<<31; /* enable */ < loadreg(igfx, p->fdi->txctl); --- > p->fdi->txctl.v &= ~(3<<8); /* link train pattern 00 */ > p->fdi->txctl.v |= 1<<10; /* auto train enable */ > p->fdi->txctl.v |= 1<<31; /* enable */ > loadreg(igfx, p->fdi->txctl); /sys/src/cmd/aux/vga/igfx.c:1162,1186 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1115,1116 < /* wait for bit lock */ < for(i=0; i<10; i++){ < sleep(1); < if(rr(igfx, p->fdi->rxiir.a) & (1<<8)) < break; < } < csr(igfx, p->fdi->rxiir.a, 0, 1<<8); < < /* switch to link train pattern2 */ < csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8); < csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8); < < /* wait for symbol lock */ < for(i=0; i<10; i++){ < sleep(1); < if(rr(igfx, p->fdi->rxiir.a) & (1<<9)) < break; < } < csr(igfx, p->fdi->rxiir.a, 0, 1<<9); < < /* switch to link train normal */ < csr(igfx, p->fdi->rxctl.a, 0, 3<<8); < csr(igfx, p->fdi->txctl.a, 0, 3<<8); < < /* wait idle pattern time */ --- > /* wait for link training done */ > for(i=0; i<200; i++){ /sys/src/cmd/aux/vga/igfx.c:1188,1204 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1118,1119 < } else { < p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 00 */ < p->fdi->rxctl.v |= 1<<10; /* auto train enable */ < p->fdi->rxctl.v |= 1<<31; /* enable */ < loadreg(igfx, p->fdi->rxctl); < < p->fdi->txctl.v &= ~(3<<8); /* link train pattern 00 */ < p->fdi->txctl.v |= 1<<10; /* auto train enable */ < p->fdi->txctl.v |= 1<<31; /* enable */ < loadreg(igfx, p->fdi->txctl); < < /* wait for link training done */ < for(i=0; i<200; i++){ < sleep(5); < if(rr(igfx, p->fdi->txctl.a) & 2) < break; < } --- > if(rr(igfx, p->fdi->txctl.a) & 2) > break; /sys/src/cmd/aux/vga/igfx.c:1292 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1207 < csr(igfx, igfx->adpa.a, 1<<31, 0); /* disable adpa */ --- > csr(igfx, igfx->adpa.a, 1<<31, 0); /sys/src/cmd/aux/vga/igfx.c:1335,1336 d /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1249 < igfx->adpa.v &= ~(3<<10); /* Monitor DPMS: on */ < /sys/src/cmd/aux/vga/igfx.c:1798 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1712 > /sys/src/cmd/aux/vga/igfx.c:1800 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1715 > /sys/src/cmd/aux/vga/igfx.c:1818 a /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1734 > /sys/src/cmd/aux/vga/igfx.c:1840 c /n/cdrom/sys/src/cmd/aux/vga/igfx.c:1756 < wr(igfx, igfx->gmbus[GMBUSCP].a, port); /* set out device by port# */ --- > wr(igfx, igfx->gmbus[GMBUSCP].a, port); --upas-fdhzpaqcwexozjxxnuawacstnw--