From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from duke.felloff.net ([216.126.196.34]) by ur; Sat Aug 20 13:11:50 EDT 2016 Message-ID: <0f62b4626a0f8b42484f590276ab0595@felloff.net> Date: Sat, 20 Aug 2016 19:11:20 +0200 From: cinap_lenrek@felloff.net To: 9front@9front.org Subject: Re: [9front] core-i5(TypeSNB) and vesa mode In-Reply-To: <01d4f478ff2772119d71f878f3083f93@ci5dell.jitaku.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit List-ID: <9front.9front.org> List-Help: X-Glyph: ➈ X-Bullshit: non-blocking event table i'v implemented displayport and fdi lane count determination now (see needlanes() function) and tested on ivy bridge and g45 machine with displayport and LVDS. 8bpc works now :) also commited our work in progress sandy bridge code for fdi link train sequence, but havnt included the changes for the dpll stuff as they are in the wrong place and unexplained/make no sense. -- cinap