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Date: Wed, 3 Jun 2020 19:58:14 +0200
From: cinap_lenrek@felloff.net
To: 9front@9front.org
Subject: Re: [9front] 9front and raspberry pi 4 8gb model
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the firmware is loaded by the gpu. it is just that you need to issue a
firmware command to the gpu firmware after mapping the pcie devices.

richard miller sent me a patch, his toubleshooting is documented here:

https://github.com/raspberrypi/firmware/issues/1402

the adapted and untested patch for 9front is below.

if you have a pi4 with 8GB, it would be great if you can try it.

just apply the patch below and build a kernel in /sys/src/9/bcm64
with: 'mk CONF=pi4'. or you can try out the kernels i'v just build:

http://felloff.net/usr/cinap_lenrek/9pi4 (raw kernel)
http://felloff.net/usr/cinap_lenrek/s9pi4 (a.out with debug symbols)

the resulting 9pi4 raw kernel can be put into the sdcard image
from the latest release.

diff -r ff6b294d07a9 sys/src/9/bcm/vcore.c
--- a/sys/src/9/bcm/vcore.c	Mon Jun 01 00:07:01 2020 +0200
+++ b/sys/src/9/bcm/vcore.c	Wed Jun 03 19:17:09 2020 +0200
@@ -53,6 +53,7 @@
 	TagSetEgpioConf	= 0x00038043,
 
 	TagGettemp	= 0x00030006,
+	TagXhciReset	= 0x00030058,
 	TagFballoc	= 0x00040001,
 	TagFbfree	= 0x00048001,
 	TagFbblank	= 0x00040002,
@@ -413,3 +414,19 @@
 	buf[1] = on;
 	vcreq(TagSetEgpioState, buf, sizeof(buf), sizeof(buf));
 }
+
+/*
+ * Notify gpu that xhci firmware might need loading. This is for some
+ * pi4 board versions which are missing the eeprom chip for the vl805,
+ * requiring its firmware to come from the boot eeprom instead.
+ */
+int
+xhcireset(int devaddr)
+{
+	u32int buf[1];
+
+	buf[0] = devaddr;
+	if(vcreq(TagXhciReset, buf, sizeof(buf), sizeof(buf[0])) == sizeof(buf[0]))
+		return buf[0];
+	return -1;
+}
diff -r ff6b294d07a9 sys/src/9/bcm64/archbcm4.c
--- a/sys/src/9/bcm64/archbcm4.c	Mon Jun 01 00:07:01 2020 +0200
+++ b/sys/src/9/bcm64/archbcm4.c	Wed Jun 03 19:55:12 2020 +0200
@@ -172,5 +172,20 @@
 void
 archbcm4link(void)
 {
+	Pcidev *p;
+
+	/*
+	 * The firmware resets PCI before starting the host OS because
+	 * without SDRAM the VL805 makes inbound requests to page-in firmware
+	 * from SDRAM. If the OS has a different PCI mapping that would all break.
+	 * There's no way to pause and move the mappings and it's not really desirable
+	 * for the firmware to dictate the PCI configuration. Consequently, the mailbox
+	 * is required so that the OS can reset the VLI after asserting PCI chip reset.
+	 */
+	if((p = pcimatch(nil, 0x1106, 0x3483)) != nil){
+		iprint("VL805 reset...\n");
+		xhcireset(BUSBNO(p->tbdf)<<20 | BUSDNO(p->tbdf)<<15 | BUSFNO(p->tbdf)<<12);
+	}
+
 	// addclock0link(wdogfeed, HZ);
 }
diff -r ff6b294d07a9 sys/src/9/bcm64/fns.h
--- a/sys/src/9/bcm64/fns.h	Mon Jun 01 00:07:01 2020 +0200
+++ b/sys/src/9/bcm64/fns.h	Wed Jun 03 19:17:09 2020 +0200
@@ -170,6 +170,7 @@
 extern void vgpinit(void);
 extern void vgpset(uint port, int on);
 extern void egpset(uint port, int on);
+extern int xhcireset(int devaddr);
 
 /* bootargs */
 extern void bootargsinit(uintptr);
diff -r ff6b294d07a9 sys/src/9/bcm64/pi4
--- a/sys/src/9/bcm64/pi4	Mon Jun 01 00:07:01 2020 +0200
+++ b/sys/src/9/bcm64/pi4	Wed Jun 03 19:17:09 2020 +0200
@@ -27,11 +27,11 @@
 link
 	gisb
 	pci
-	archbcm4
+	archbcm4	pci
+	usbxhci		pci archbcm4
 	ethergenet	ethermii
 	ethermedium
 	loopbackmedium
-	usbxhci		pci
 
 ip
 	tcp

--
cinap