From: ori@eigenstate.org
To: 9front@9front.org
Subject: Re: [9front] Weird >>= operator behaviour in 5c/5l
Date: Wed, 20 Jan 2021 15:39:46 -0800 [thread overview]
Message-ID: <15A55C95692154CE1181D48C7964AC44@eigenstate.org> (raw)
In-Reply-To: <YAiqktwGeH3ONmmB@alice>
> This will affect any assembler source that uses
>
> ROR $0, R1, R2
>
> to get at the special RRX arm instruction alias
> for a rotate right by one bit with extension.
>
> That instruction would become
>
> SRA $0, R1, R2
>
> for a arithmetic shift right by 32 bits. It's
> probably not used anywhere but I wanted to make
> sure you knew about it.
>
> For reference, here's my understanding of the
> possible shift values on arm:
>
> a i stype imm5
> SLL LSL 00 0..31
> SRL LSR 01 1..32 mod 32
> SRA ASR 10 1..32 mod 32
> ROR ROR 11 1..31
> ROR RRX 11 0
>
> Hope that helps.
>
> Cheers,
> Anthony
>
Yeah -- I was thinking that a 0-byte ROR would be
a no-op, and it wouldn't matter -- but I think I
made a mistake. It seems like I should just make
check explicitly for the opcodes, and substitute
in oprrr().
diff -r 01125acb5565 sys/src/cmd/5l/asm.c
--- a/sys/src/cmd/5l/asm.c Tue Jan 19 19:56:38 2021 -0800
+++ b/sys/src/cmd/5l/asm.c Wed Jan 20 15:38:43 2021 -0800
@@ -785,7 +785,10 @@
case 8: /* sll $c,[R],R -> mov (R<<$c),R */
aclass(&p->from);
- o1 = oprrr(p->as, p->scond);
+ if((p->as == ASRL || p->as == ASRA) && instoffset == 0)
+ o1 = oprrr(ASLL, p->scond);
+ else
+ o1 = oprrr(p->as, p->scond);
r = p->reg;
if(r == NREG)
r = p->to.reg;
prev parent reply other threads:[~2021-01-21 0:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-17 21:36 Jonas Amoson
2021-01-18 4:05 ` Noam Preil
2021-01-18 5:20 ` ori
2021-01-18 16:11 ` Jonas Amoson
2021-01-20 5:59 ` ori
2021-01-20 6:12 ` ori
2021-01-20 12:06 ` Jonas Amoson
2021-01-20 22:11 ` Anthony Martin
2021-01-20 23:39 ` ori [this message]
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